=> Building devel/lattice-ice40-examples-hx8k Started : Tuesday, 23 JUL 2019 at 06:36:42 UTC Platform: 5.7-DEVELOPMENT DragonFly v5.7.0.83.g49866-DEVELOPMENT #40: Sun Jun 30 03:00:04 PDT 2019 root@pkgbox64.dragonflybsd.org:/usr/obj/usr/src/sys/X86_64_GENERIC x86_64 -------------------------------------------------- -- Environment -------------------------------------------------- UNAME_r=5.6-SYNTH UNAME_m=x86_64 UNAME_p=x86_64 UNAME_v=DragonFly 5.6-SYNTH UNAME_s=DragonFly PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin SSL_NO_VERIFY_PEER=1 TERM=dumb PKG_CACHEDIR=/var/cache/pkg8 PKG_DBDIR=/var/db/pkg8 PORTSDIR=/xports LANG=C HOME=/root USER=root -------------------------------------------------- -- Options -------------------------------------------------- -------------------------------------------------- -- CONFIGURE_ENV -------------------------------------------------- MAKE=gmake XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin SHELL=/bin/sh CONFIG_SHELL=/bin/sh CCVER=gcc80 -------------------------------------------------- -- CONFIGURE_ARGS -------------------------------------------------- -------------------------------------------------- -- MAKE_ENV -------------------------------------------------- XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" -------------------------------------------------- -- MAKE_ARGS -------------------------------------------------- DESTDIR=/construction/devel/lattice-ice40-examples-hx8k/stage -------------------------------------------------- -- PLIST_SUB -------------------------------------------------- OSREL=5.6 PREFIX=%D LOCALBASE=/usr/local RESETPREFIX=/usr/local LIB32DIR=lib PROFILE="@comment " DOCSDIR="share/doc/lattice-ice40-examples-hx8k" EXAMPLESDIR="share/examples/lattice-ice40-olimex" DATADIR="share/lattice-ice40-examples-hx8k" WWWDIR="www/lattice-ice40-examples-hx8k" ETCDIR="etc/lattice-ice40-examples-hx8k" -------------------------------------------------- -- SUB_LIST -------------------------------------------------- PREFIX=/usr/local LOCALBASE=/usr/local DATADIR=/usr/local/share/lattice-ice40-examples-hx8k DOCSDIR=/usr/local/share/doc/lattice-ice40-examples-hx8k EXAMPLESDIR=/usr/local/share/examples/lattice-ice40-olimex WWWDIR=/usr/local/www/lattice-ice40-examples-hx8k ETCDIR=/usr/local/etc/lattice-ice40-examples-hx8k -------------------------------------------------- -- /etc/make.conf -------------------------------------------------- SYNTHPROFILE=Release-5.6 USE_PACKAGE_DEPENDS_ONLY=yes PACKAGE_BUILDING=yes BATCH=yes PKG_CREATE_VERBOSE=yes PORTSDIR=/xports DISTDIR=/distfiles WRKDIRPREFIX=/construction PORT_DBDIR=/options PACKAGES=/packages MAKE_JOBS_NUMBER_LIMIT=5 LICENSES_ACCEPTED= NONE HAVE_COMPAT_IA32_KERN= CONFIGURE_MAX_CMD_LEN=262144 _PERL5_FROM_BIN=5.28.1 _ALTCCVERSION_921dbbb2=none _OBJC_ALTCCVERSION_921dbbb2=none _SMP_CPUS=8 UID=0 ARCH=x86_64 OPSYS=DragonFly DFLYVERSION=500601 OSVERSION=9999999 OSREL=5.6 _OSRELEASE=5.6-SYNTH PYTHONBASE=/usr/local _PKG_CHECKED=1 -------------------------------------------------------------------------------- -- Phase: check-sanity -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user -------------------------------------------------------------------------------- -- Phase: pkg-depends -------------------------------------------------------------------------------- ===> lattice-ice40-examples-hx8k-g20180310 depends on file: /usr/local/sbin/pkg - not found ===> Installing existing package /packages/All/pkg-1.11.1.txz Installing pkg-1.11.1... Extracting pkg-1.11.1: .......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on file: /usr/local/sbin/pkg - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: fetch-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: fetch -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310 for building -------------------------------------------------------------------------------- -- Phase: checksum -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310 for building => SHA256 Checksum OK for OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz. -------------------------------------------------------------------------------- -- Phase: extract-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: extract -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310 for building ===> Extracting for lattice-ice40-examples-hx8k-g20180310 => SHA256 Checksum OK for OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz. -------------------------------------------------------------------------------- -- Phase: patch-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: patch -------------------------------------------------------------------------------- ===> Patching for lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: build-depends -------------------------------------------------------------------------------- ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: abc - not found ===> Installing existing package /packages/All/abc-g20180420_1.txz Installing abc-g20180420_1... `-- Installing readline-8.0.0... | `-- Installing indexinfo-0.3.1... | `-- Extracting indexinfo-0.3.1: .... done | `-- Installing ncurses-6.1.20190525... | `-- Extracting ncurses-6.1.20190525: .......... done `-- Extracting readline-8.0.0: .......... done Extracting abc-g20180420_1: ....... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: abc - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: arachne-pnr - not found ===> Installing existing package /packages/All/arachne-pnr-g20181021_1.txz Installing arachne-pnr-g20181021_1... Extracting arachne-pnr-g20181021_1: ......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: arachne-pnr - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: icepack - not found ===> Installing existing package /packages/All/icestorm-g20190526.txz Installing icestorm-g20190526... `-- Installing libftdi1-1.4_11... | `-- Installing boost-libs-1.70.0_2... | | `-- Installing icu-64.2,1... | | `-- Extracting icu-64.2,1: .......... done | `-- Extracting boost-libs-1.70.0_2: .......... done | `-- Installing gettext-runtime-0.20.1... | `-- Extracting gettext-runtime-0.20.1: .......... done | `-- Installing libconfuse-3.2.1_1... | `-- Extracting libconfuse-3.2.1_1: .......... done | `-- Installing python27-2.7.16_1... | | `-- Installing expat-2.2.6_1... | | `-- Extracting expat-2.2.6_1: .......... done | | `-- Installing libffi-3.2.1_3... | | `-- Extracting libffi-3.2.1_3: .......... done | | `-- Installing libressl-2.9.2... | | `-- Extracting libressl-2.9.2: .......... done | `-- Extracting python27-2.7.16_1: .......... done `-- Extracting libftdi1-1.4_11: .......... done `-- Installing py36-boost-libs-1.70.0_2... | `-- Installing python36-3.6.9... | `-- Extracting python36-3.6.9: .......... done `-- Extracting py36-boost-libs-1.70.0_2: .......... done Extracting icestorm-g20190526: .......... done Message from boost-libs-1.70.0_2: You have built the Boost library with thread support. Don't forget to add -pthread to your linker options when linking your code. Message from python27-2.7.16_1: =========================================================================== Note that some standard Python modules are provided as separate ports as they require additional dependencies. They are available as: bsddb databases/py-bsddb gdbm databases/py-gdbm sqlite3 databases/py-sqlite3 tkinter x11-toolkits/py-tkinter =========================================================================== Message from python36-3.6.9: =========================================================================== Note that some standard Python modules are provided as separate ports as they require additional dependencies. They are available as: py36-gdbm databases/py-gdbm@py36 py36-sqlite3 databases/py-sqlite3@py36 py36-tkinter x11-toolkits/py-tkinter@py36 =========================================================================== Message from py36-boost-libs-1.70.0_2: You have built the Boost library with thread support. Don't forget to add -pthread to your linker options when linking your code. You have built the Boost.Python library. You have to add the following options when building your own code: Compiler options: -I/usr/local/include/python3.6m -I/usr/local/include Linker options: -L/usr/local/lib/python3.6 -L/usr/local/lib -lboost_python -lpython3.6 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: icepack - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: yosys - not found ===> Installing existing package /packages/All/yosys-0.8.1116.txz Installing yosys-0.8.1116... `-- Installing tcl86-8.6.9_1... `-- Extracting tcl86-8.6.9_1: .......... done Extracting yosys-0.8.1116: .......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: yosys - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: gmake - not found ===> Installing existing package /packages/All/gmake-4.2.1_3.txz Installing gmake-4.2.1_3... Extracting gmake-4.2.1_3: .......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: gmake - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: lib-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: configure -------------------------------------------------------------------------------- ===> Configuring for lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: build -------------------------------------------------------------------------------- ===> Building for lattice-ice40-examples-hx8k-g20180310 /usr/bin/env XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -j5 -C /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb gmake[1]: Entering directory '/construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb' yosys -p 'synth_ice40 -top top -blif example.blif' example.v /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8+ (git sha1 UNKNOWN, c++ 8.3 -O2 -fno-strict-aliasing -fPIC -Os) -- Parsing `example.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend: example.v Parsing Verilog input from `example.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. -- Running command `synth_ice40 -top top -blif example.blif' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Analyzing design hierarchy.. Top module: \top 2.2.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$example.v:23$20'. Set init value: \mode = 1'1 Found init rule in `\top.$proc$example.v:22$19'. Set init value: \rst_cnt = 15'000000000000000 2.3.4. Executing PROC_ARST pass (detect async resets in processes). 2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$proc$example.v:23$20'. 1/1: $1\mode[0:0] Creating decoders for process `\top.$proc$example.v:22$19'. 1/1: $1\rst_cnt[14:0] Creating decoders for process `\top.$proc$example.v:38$5'. 1/9: $0\LED2_m0_r[0:0] 2/9: $0\LED1_m0_r[0:0] 3/9: $0\cntr[14:0] 4/9: $0\BUT2_r[0:0] 5/9: $0\BUT1_r[0:0] 6/9: $0\mode[0:0] 7/9: $0\rst_cnt[14:0] 8/9: $0\LED2_m1_r[0:0] 9/9: $0\LED1_m1_r[0:0] Creating decoders for process `\top.$proc$example.v:34$3'. 1/1: $0\clk_div[11:0] 2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\LED1_m0_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$37' with positive edge clock. Creating register for signal `\top.\LED2_m0_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$38' with positive edge clock. Creating register for signal `\top.\LED1_m1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$39' with positive edge clock. Creating register for signal `\top.\BUT1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$40' with positive edge clock. Creating register for signal `\top.\BUT2_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$41' with positive edge clock. Creating register for signal `\top.\LED2_m1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$42' with positive edge clock. Creating register for signal `\top.\cntr' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$43' with positive edge clock. Creating register for signal `\top.\rst_cnt' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$44' with positive edge clock. Creating register for signal `\top.\mode' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$45' with positive edge clock. Creating register for signal `\top.\clk_div' using process `\top.$proc$example.v:34$3'. created $dff cell `$procdff$46' with positive edge clock. 2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$proc$example.v:23$20'. Removing empty process `top.$proc$example.v:22$19'. Found and cleaned up 4 empty switches in `\top.$proc$example.v:38$5'. Removing empty process `top.$proc$example.v:38$5'. Removing empty process `top.$proc$example.v:34$3'. Cleaned up 4 empty switches. 2.4. Executing FLATTEN pass (flatten design). No more expansions possible. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 24 unused wires. 2.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 2 cells. 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $procmux$25: \rst_cnt -> { 1'1 \rst_cnt [13:0] } Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. 2.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.9. Finished OPT passes. (There is nothing left to do.) 2.11. Executing WREDUCE pass (reducing word size of cells). Removed top 11 bits (of 12) from port B of cell top.$add$example.v:35$4 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:41$6 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:44$8 ($add). Removed top 1 bits (of 15) from port B of cell top.$eq$example.v:55$17 ($eq). 2.12. Executing PEEPOPT pass (run peephole optimizers). 2.13. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.14. Executing SHARE pass (SAT-based resource sharing). 2.15. Executing TECHMAP pass (map to technology primitives). 2.15.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.15.2. Continuing TECHMAP pass. No more expansions possible. 2.16. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.18. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $add$example.v:35$4 ($add). creating $macc model for $add$example.v:41$6 ($add). creating $macc model for $add$example.v:44$8 ($add). creating $alu model for $macc $add$example.v:44$8. creating $alu model for $macc $add$example.v:41$6. creating $alu model for $macc $add$example.v:35$4. creating $alu model for $gt$example.v:59$18 ($gt): new $alu creating $alu cell for $gt$example.v:59$18: $auto$alumacc.cc:474:replace_alu$48 creating $alu cell for $add$example.v:35$4: $auto$alumacc.cc:474:replace_alu$59 creating $alu cell for $add$example.v:41$6: $auto$alumacc.cc:474:replace_alu$62 creating $alu cell for $add$example.v:44$8: $auto$alumacc.cc:474:replace_alu$65 created 4 $alu and 0 $macc cells. 2.19. Executing OPT pass (performing simple optimizations). 2.19.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$51: { $auto$alumacc.cc:490:replace_alu$49 [0] $auto$alumacc.cc:490:replace_alu$49 [1] $auto$alumacc.cc:490:replace_alu$49 [2] $auto$alumacc.cc:490:replace_alu$49 [3] $auto$alumacc.cc:490:replace_alu$49 [4] $auto$alumacc.cc:490:replace_alu$49 [5] $auto$alumacc.cc:490:replace_alu$49 [6] $auto$alumacc.cc:490:replace_alu$49 [7] $auto$alumacc.cc:490:replace_alu$49 [8] $auto$alumacc.cc:490:replace_alu$49 [9] $auto$alumacc.cc:490:replace_alu$49 [10] $auto$alumacc.cc:490:replace_alu$49 [11] $auto$alumacc.cc:490:replace_alu$49 [12] $auto$alumacc.cc:490:replace_alu$49 [13] $auto$alumacc.cc:490:replace_alu$49 [14] } Optimizing cells in module \top. Performed a total of 1 changes. 2.19.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.19.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.19.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 2 unused wires. 2.19.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19.9. Rerunning OPT passes. (Maybe there is more to do..) 2.19.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.19.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.19.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.19.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.19.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.19.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19.16. Finished OPT passes. (There is nothing left to do.) 2.20. Executing FSM pass (extract and optimize FSM). 2.20.1. Executing FSM_DETECT pass (finding FSMs in design). 2.20.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.20.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.20.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.20.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.20.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.20.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.20.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.21. Executing OPT pass (performing simple optimizations). 2.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.21.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.21.5. Finished fast OPT passes. 2.22. Executing MEMORY pass. 2.22.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 2.22.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.22.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.22.5. Executing MEMORY_COLLECT pass (generating $mem cells). 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). 2.25. Executing TECHMAP pass (map to technology primitives). 2.25.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 2.25.2. Continuing TECHMAP pass. No more expansions possible. 2.26. Executing ICE40_BRAMINIT pass. 2.27. Executing OPT pass (performing simple optimizations). 2.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.27.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.27.5. Finished fast OPT passes. 2.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 2.29. Executing OPT pass (performing simple optimizations). 2.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.9. Finished OPT passes. (There is nothing left to do.) 2.30. Executing TECHMAP pass (map to technology primitives). 2.30.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.30.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.30.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=15\Y_WIDTH=15 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=15\B_WIDTH=15\Y_WIDTH=15 for cells of type $alu. Using extmapper simplemap for cells of type $or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=12\Y_WIDTH=12 for cells of type $alu. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.31. Executing ICE40_OPT pass (performing simple optimizations). 2.31.1. Running ICE40 specific optimizations. 2.31.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 5 cells. 2.31.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 63 unused cells and 70 unused wires. 2.31.6. Rerunning OPT passes. (Removed registers in this run.) 2.31.7. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$48.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$59.slice[0].carry: CO=\clk_div [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$62.slice[0].carry: CO=\cntr [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$65.slice[0].carry: CO=\rst_cnt [0] Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$59.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$62.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$65.slice[1].adder back to logic. 2.31.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 9 unused wires. 2.31.12. Rerunning OPT passes. (Removed registers in this run.) 2.31.13. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$48.slice[1].carry: CO=\cntr [1] 2.31.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.16. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.18. Rerunning OPT passes. (Removed registers in this run.) 2.31.19. Running ICE40 specific optimizations. 2.31.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.22. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.24. Finished OPT passes. (There is nothing left to do.) 2.32. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). 2.33. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). Selected cell types for direct conversion: $_DFF_PP1_ -> $__DFFE_PP1 $_DFF_PP0_ -> $__DFFE_PP0 $_DFF_PN1_ -> $__DFFE_PN1 $_DFF_PN0_ -> $__DFFE_PN0 $_DFF_NP1_ -> $__DFFE_NP1 $_DFF_NP0_ -> $__DFFE_NP0 $_DFF_NN1_ -> $__DFFE_NN1 $_DFF_NN0_ -> $__DFFE_NN0 $_DFF_N_ -> $_DFFE_NP_ $_DFF_P_ -> $_DFFE_PP_ Transforming FF to FF+Enable cells in module top: converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$245 to $_DFFE_PP_ for $0\LED1_m1_r[0:0] -> \LED1_m1_r. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$248 to $_DFFE_PP_ for $0\LED2_m1_r[0:0] -> \LED2_m1_r. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$250 to $_DFFE_PP_ for $0\cntr[14:0] [1] -> \cntr [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$264 to $_DFFE_PP_ for $0\rst_cnt[14:0] [0] -> \rst_cnt [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$265 to $_DFFE_PP_ for $0\rst_cnt[14:0] [1] -> \rst_cnt [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$266 to $_DFFE_PP_ for $0\rst_cnt[14:0] [2] -> \rst_cnt [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$267 to $_DFFE_PP_ for $0\rst_cnt[14:0] [3] -> \rst_cnt [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$268 to $_DFFE_PP_ for $0\rst_cnt[14:0] [4] -> \rst_cnt [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$269 to $_DFFE_PP_ for $0\rst_cnt[14:0] [5] -> \rst_cnt [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$270 to $_DFFE_PP_ for $0\rst_cnt[14:0] [6] -> \rst_cnt [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$271 to $_DFFE_PP_ for $0\rst_cnt[14:0] [7] -> \rst_cnt [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$272 to $_DFFE_PP_ for $0\rst_cnt[14:0] [8] -> \rst_cnt [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$273 to $_DFFE_PP_ for $0\rst_cnt[14:0] [9] -> \rst_cnt [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$274 to $_DFFE_PP_ for $0\rst_cnt[14:0] [10] -> \rst_cnt [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$275 to $_DFFE_PP_ for $0\rst_cnt[14:0] [11] -> \rst_cnt [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$276 to $_DFFE_PP_ for $0\rst_cnt[14:0] [12] -> \rst_cnt [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$277 to $_DFFE_PP_ for $0\rst_cnt[14:0] [13] -> \rst_cnt [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$279 to $_DFFE_PP_ for $0\mode[0:0] -> \mode. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$281 to $_DFFE_PP_ for $0\clk_div[11:0] [1] -> \clk_div [1]. 2.34. Executing TECHMAP pass (map to technology primitives). 2.34.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Successfully finished Verilog frontend. 2.34.2. Continuing TECHMAP pass. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. No more expansions possible. 2.35. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.36. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.37. Executing ICE40_FFINIT pass (implement FF init values). Handling FF init values in top. FF init value for cell $auto$simplemap.cc:420:simplemap_dff$264 (SB_DFFE): \rst_cnt [0] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$265 (SB_DFFE): \rst_cnt [1] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$266 (SB_DFFE): \rst_cnt [2] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$267 (SB_DFFE): \rst_cnt [3] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$268 (SB_DFFE): \rst_cnt [4] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$269 (SB_DFFE): \rst_cnt [5] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$270 (SB_DFFE): \rst_cnt [6] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$271 (SB_DFFE): \rst_cnt [7] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$273 (SB_DFFE): \rst_cnt [9] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$274 (SB_DFFE): \rst_cnt [10] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$275 (SB_DFFE): \rst_cnt [11] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$276 (SB_DFFE): \rst_cnt [12] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$277 (SB_DFFE): \rst_cnt [13] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$278 (SB_DFF): \rst_cnt [14] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$279 (SB_DFFE): \mode = 1 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$272 (SB_DFFE): \rst_cnt [8] = 0 2.38. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells). Merging set/reset $_MUX_ cells into SB_FFs in top. Merging $auto$simplemap.cc:277:simplemap_mux$209 (A=1'0, B=$add$example.v:41$6_Y [7], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$256 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$203 (A=1'0, B=$auto$simplemap.cc:309:simplemap_lut$496 [1], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$250 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$204 (A=1'0, B=$add$example.v:41$6_Y [2], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$251 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$205 (A=1'0, B=$add$example.v:41$6_Y [3], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$252 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$206 (A=1'0, B=$add$example.v:41$6_Y [4], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$253 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$207 (A=1'0, B=$add$example.v:41$6_Y [5], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$254 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$208 (A=1'0, B=$add$example.v:41$6_Y [6], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$255 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$210 (A=1'0, B=$add$example.v:41$6_Y [8], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$257 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$211 (A=1'0, B=$add$example.v:41$6_Y [9], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$258 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$212 (A=1'0, B=$add$example.v:41$6_Y [10], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$259 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$213 (A=1'0, B=$add$example.v:41$6_Y [11], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$260 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$214 (A=1'0, B=$add$example.v:41$6_Y [12], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$261 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$215 (A=1'0, B=$add$example.v:41$6_Y [13], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$262 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$216 (A=1'0, B=$add$example.v:41$6_Y [14], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$263 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$221 (A=$add$example.v:44$8_Y [0], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$264 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$222 (A=$auto$simplemap.cc:309:simplemap_lut$515 [1], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$265 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$223 (A=$add$example.v:44$8_Y [2], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$266 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$224 (A=$add$example.v:44$8_Y [3], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$267 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$225 (A=$add$example.v:44$8_Y [4], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$268 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$226 (A=$add$example.v:44$8_Y [5], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$269 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$227 (A=$add$example.v:44$8_Y [6], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$270 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$202 (A=1'0, B=$add$example.v:41$6_Y [0], S=$auto$rtlil.cc:1836:Or$56) into $auto$simplemap.cc:420:simplemap_dff$249 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$228 (A=$add$example.v:44$8_Y [7], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$271 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$230 (A=$add$example.v:44$8_Y [9], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$273 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$231 (A=$add$example.v:44$8_Y [10], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$274 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$232 (A=$add$example.v:44$8_Y [11], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$275 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$233 (A=$add$example.v:44$8_Y [12], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$276 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$234 (A=$add$example.v:44$8_Y [13], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$277 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$235 (A=$procmux$25_Y [14], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$278 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$229 (A=$add$example.v:44$8_Y [8], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$272 (SB_DFFE). 2.39. Executing ICE40_OPT pass (performing simple optimizations). 2.39.1. Running ICE40 specific optimizations. 2.39.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 45 cells. 2.39.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 30 unused cells and 243 unused wires. 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 2.39.7. Running ICE40 specific optimizations. 2.39.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.39.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.39.12. Finished OPT passes. (There is nothing left to do.) 2.40. Executing TECHMAP pass (map to technology primitives). 2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 2.40.2. Continuing TECHMAP pass. No more expansions possible. 2.41. Executing ABC pass (technology mapping using ABC). 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. Extracted 64 gates and 93 wires to a netlist network with 28 inputs and 16 outputs. 2.41.1.1. Executing ABC. Running ABC command: abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + retime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 17. ABC: Participating nodes from both networks = 39. ABC: Participating nodes from the first network = 17. ( 68.00 % of nodes) ABC: Participating nodes from the second network = 22. ( 88.00 % of nodes) ABC: Node pairs (any polarity) = 17. ( 68.00 % of names can be moved) ABC: Node pairs (same polarity) = 16. ( 64.00 % of names can be moved) ABC: Total runtime = 0.00 sec ABC: + write_blif /output.blif 2.41.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 48 ABC RESULTS: internal signals: 49 ABC RESULTS: input signals: 28 ABC RESULTS: output signals: 16 Removing temp directory. Removed 0 unused cells and 58 unused wires. 2.42. Executing TECHMAP pass (map to technology primitives). 2.42.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.42.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101111111000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. No more expansions possible. Removed 0 unused cells and 48 unused wires. 2.43. Executing HIERARCHY pass (managing design hierarchy). 2.43.1. Analyzing design hierarchy.. Top module: \top 2.43.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.44. Printing statistics. === top === Number of wires: 48 Number of wire bits: 179 Number of public wires: 17 Number of public wire bits: 56 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 161 SB_CARRY 49 SB_DFF 15 SB_DFFE 4 SB_DFFESR 15 SB_DFFSR 15 SB_LUT4 63 2.45. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.46. Executing BLIF backend. End of script. Logfile hash: 3456974dab CPU: user 0.76s system 0.03s, MEM: 56.64 MB total, 48.05 MB resident Yosys 0.8+ (git sha1 UNKNOWN, c++ 8.3 -O2 -fno-strict-aliasing -fPIC -Os) Time spent: 42% 10x read_verilog (0 sec), 14% 19x opt_clean (0 sec), ... arachne-pnr -d 8k -o example.asc -p ice40hx8k-evb.pcf example.blif -P ct256 seed: 1 device: 8k read_chipdb +/share/arachne-pnr/chipdb-8k.bin... supported packages: bg121, bg121:4k, cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k read_blif example.blif... prune... read_pcf ice40hx8k-evb.pcf... instantiate_io... pack... After packing: IOs 5 / 206 GBs 0 / 8 GB_IOs 0 / 8 LCs 88 / 7680 DFF 16 CARRY 20 CARRY, DFF 33 DFF PASS 3 CARRY PASS 6 BRAMs 0 / 32 WARMBOOTs 0 / 1 PLLs 0 / 2 place_constraints... promote_globals... promoted clk_24KHz, 38 / 38 promoted $abc$797$auto$dff2dffe.cc:158:make_patterns_logic$689, 17 / 18 promoted $0\LED1_m1_r[0:0], 16 / 16 promoted $abc$797$auto$dff2dffe.cc:158:make_patterns_logic$547, 13 / 13 promoted CLK$2, 12 / 12 promoted 5 nets 2 sr/we 1 cen/wclke 2 clk 5 globals 2 sr/we 1 cen/wclke 2 clk realize_constants... realized 1 place... initial wire length = 1614 at iteration #50: temp = 16.6458, wire length = 851 at iteration #100: temp = 8.545, wire length = 620 at iteration #150: temp = 3.76088, wire length = 368 at iteration #200: temp = 1.15593, wire length = 226 final wire length = 185 After placement: PIOs 8 / 206 PLBs 24 / 960 BRAMs 0 / 32 place time 0.29s route... pass 1, 0 shared. After routing: span_4 38 / 29696 span_12 13 / 5632 route time 0.26s write_txt example.asc... icetime -d hx8k -mtr example.rpt example.asc icepack example.asc example.bin // Reading input .asc file.. // Reading 8k chipdb file.. // Creating timing netlist.. // Timing estimate: 7.72 ns (129.59 MHz) rm example.blif example.asc gmake[1]: Leaving directory '/construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb' /usr/bin/env XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -j5 -C /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video gmake[1]: Entering directory '/construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video' yosys -p 'synth_ice40 -top top -blif example.blif' example.v /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8+ (git sha1 UNKNOWN, c++ 8.3 -O2 -fno-strict-aliasing -fPIC -Os) -- Parsing `example.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend: example.v Parsing Verilog input from `example.v' to AST representation. Generating RTLIL representation for module `\top'. Warning: Replacing memory \sq_figure with list of registers. See example.v:126 Successfully finished Verilog frontend. -- Running command `synth_ice40 -top top -blif example.blif' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Analyzing design hierarchy.. Top module: \top 2.2.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 21 switch rules as full_case in process $proc$example.v:110$16 in module top. Removed a total of 0 dead cases. 2.3.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$example.v:96$109'. Set init value: \r_arr = 1'0 Found init rule in `\top.$proc$example.v:95$108'. Set init value: \d_arr = 1'0 Found init rule in `\top.$proc$example.v:94$107'. Set init value: \l_arr = 1'0 Found init rule in `\top.$proc$example.v:93$106'. Set init value: \u_arr = 1'0 Found init rule in `\top.$proc$example.v:63$105'. Set init value: \reset = 1'1 Found init rule in `\top.$proc$example.v:62$104'. Set init value: \timer_t = 8'00000000 2.3.4. Executing PROC_ARST pass (detect async resets in processes). 2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$proc$example.v:96$109'. 1/1: $1\r_arr[0:0] Creating decoders for process `\top.$proc$example.v:95$108'. 1/1: $1\d_arr[0:0] Creating decoders for process `\top.$proc$example.v:94$107'. 1/1: $1\l_arr[0:0] Creating decoders for process `\top.$proc$example.v:93$106'. 1/1: $1\u_arr[0:0] Creating decoders for process `\top.$proc$example.v:63$105'. 1/1: $1\reset[0:0] Creating decoders for process `\top.$proc$example.v:62$104'. 1/1: $1\timer_t[7:0] Creating decoders for process `\top.$proc$example.v:110$16'. 1/73: $0\ps2_data_reg[7:0] [7] 2/73: $1$mem2bits$\sq_figure$example.v:308$4[19:0]$89 3/73: $1$mem2bits$\sq_figure$example.v:307$3[19:0]$88 4/73: $1$mem2bits$\sq_figure$example.v:306$2[19:0]$87 5/73: $0\ps2_data_reg[7:0] [4] 6/73: $1$mem2bits$\sq_figure$example.v:309$5[19:0]$90 7/73: $0\ps2_data_reg[7:0] [5] 8/73: $0\ps2_data_reg[7:0] [6] 9/73: $0\ps2_data_reg[7:0] [0] 10/73: $0\ps2_data_reg[7:0] [1] 11/73: $0\ps2_data_reg[7:0] [2] 12/73: $0\ps2_data_reg[7:0] [3] 13/73: $3$mem2bits$\sq_figure$example.v:202$1[19:0]$65 14/73: $3$mem2reg_rd$\sq_figure$example.v:202$6_DATA[19:0]$67 15/73: $3$mem2reg_rd$\sq_figure$example.v:202$6_ADDR[4:0]$66 16/73: $2$mem2reg_rd$\sq_figure$example.v:202$6_DATA[19:0]$57 17/73: $2$mem2reg_rd$\sq_figure$example.v:202$6_ADDR[4:0]$56 18/73: $2$mem2bits$\sq_figure$example.v:202$1[19:0]$55 19/73: $1$mem2reg_rd$\sq_figure$example.v:202$6_DATA[19:0]$47 20/73: $1$mem2reg_rd$\sq_figure$example.v:202$6_ADDR[4:0]$46 21/73: $1$mem2bits$\sq_figure$example.v:202$1[19:0]$45 22/73: $0$mem2bits$\sq_figure$example.v:309$5[19:0]$21 23/73: $0$mem2bits$\sq_figure$example.v:308$4[19:0]$20 24/73: $0$mem2bits$\sq_figure$example.v:307$3[19:0]$19 25/73: $0$mem2bits$\sq_figure$example.v:306$2[19:0]$18 26/73: $0\arr_timer[20:0] 27/73: $0\ps2_clk_buf[1:0] 28/73: $0$mem2reg_rd$\sq_figure$example.v:202$6_DATA[19:0]$23 29/73: $0$mem2reg_rd$\sq_figure$example.v:202$6_ADDR[4:0]$22 30/73: $0$mem2bits$\sq_figure$example.v:202$1[19:0]$17 31/73: $0\sq_figure[19][19:0] 32/73: $0\sq_figure[18][19:0] 33/73: $0\sq_figure[17][19:0] 34/73: $0\sq_figure[16][19:0] 35/73: $0\sq_figure[15][19:0] 36/73: $0\sq_figure[14][19:0] 37/73: $0\sq_figure[13][19:0] 38/73: $0\sq_figure[12][19:0] 39/73: $0\sq_figure[11][19:0] 40/73: $0\sq_figure[10][19:0] 41/73: $0\sq_figure[9][19:0] 42/73: $0\sq_figure[8][19:0] 43/73: $0\sq_figure[7][19:0] 44/73: $0\sq_figure[6][19:0] 45/73: $0\sq_figure[5][19:0] 46/73: $0\sq_figure[4][19:0] 47/73: $0\sq_figure[3][19:0] 48/73: $0\sq_figure[2][19:0] 49/73: $0\sq_figure[1][19:0] 50/73: $0\sq_figure[0][19:0] 51/73: $0\r_arr[0:0] 52/73: $0\d_arr[0:0] 53/73: $0\l_arr[0:0] 54/73: $0\u_arr[0:0] 55/73: $0\ps2_dat_r[10:0] 56/73: $0\ps2_data_reg_prev1[7:0] 57/73: $0\ps2_data_reg_prev[7:0] 58/73: $4$mem2reg_rd$\sq_figure$example.v:202$6_DATA[19:0]$68 59/73: $0\ps2_cntr[3:0] 60/73: $0\sq_pos_y[9:0] 61/73: $0\sq_pos_x[9:0] 62/73: $0\disp_en[0:0] 63/73: $0\c_ver[9:0] 64/73: $0\c_hor[9:0] 65/73: $0\c_col[9:0] 66/73: $0\c_row[9:0] 67/73: $0\reset[0:0] 68/73: $0\timer_t[7:0] 69/73: $0\vga_vs_r[0:0] 70/73: $0\vga_hs_r[0:0] 71/73: $0\vga_b_r[2:0] 72/73: $0\vga_g_r[2:0] 73/73: $0\vga_r_r[2:0] Creating decoders for process `\top.$proc$example.v:46$7'. 1/1: $0\clk_div[1:0] 2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\vga_r_r' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$680' with positive edge clock. Creating register for signal `\top.\vga_g_r' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$681' with positive edge clock. Creating register for signal `\top.\vga_b_r' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$682' with positive edge clock. Creating register for signal `\top.\vga_hs_r' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$683' with positive edge clock. Creating register for signal `\top.\vga_vs_r' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$684' with positive edge clock. Creating register for signal `\top.\timer_t' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$685' with positive edge clock. Creating register for signal `\top.\reset' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$686' with positive edge clock. Creating register for signal `\top.\c_row' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$687' with positive edge clock. Creating register for signal `\top.\c_col' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$688' with positive edge clock. Creating register for signal `\top.\c_hor' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$689' with positive edge clock. Creating register for signal `\top.\c_ver' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$690' with positive edge clock. Creating register for signal `\top.\disp_en' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$691' with positive edge clock. Creating register for signal `\top.\sq_pos_x' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$692' with positive edge clock. Creating register for signal `\top.\sq_pos_y' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$693' with positive edge clock. Creating register for signal `\top.\ps2_cntr' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$694' with positive edge clock. Creating register for signal `\top.\ps2_data_reg' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$695' with positive edge clock. Creating register for signal `\top.\ps2_data_reg_prev' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$696' with positive edge clock. Creating register for signal `\top.\ps2_data_reg_prev1' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$697' with positive edge clock. Creating register for signal `\top.\ps2_dat_r' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$698' with positive edge clock. Creating register for signal `\top.\ps2_clk_buf' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$699' with positive edge clock. Creating register for signal `\top.\u_arr' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$700' with positive edge clock. Creating register for signal `\top.\l_arr' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$701' with positive edge clock. Creating register for signal `\top.\d_arr' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$702' with positive edge clock. Creating register for signal `\top.\r_arr' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$703' with positive edge clock. Creating register for signal `\top.\arr_timer' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$704' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:202$1' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$705' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:306$2' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$706' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:307$3' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$707' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:308$4' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$708' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:309$5' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$709' with positive edge clock. Creating register for signal `\top.\sq_figure[0]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$710' with positive edge clock. Creating register for signal `\top.\sq_figure[1]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$711' with positive edge clock. Creating register for signal `\top.\sq_figure[2]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$712' with positive edge clock. Creating register for signal `\top.\sq_figure[3]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$713' with positive edge clock. Creating register for signal `\top.\sq_figure[4]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$714' with positive edge clock. Creating register for signal `\top.\sq_figure[5]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$715' with positive edge clock. Creating register for signal `\top.\sq_figure[6]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$716' with positive edge clock. Creating register for signal `\top.\sq_figure[7]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$717' with positive edge clock. Creating register for signal `\top.\sq_figure[8]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$718' with positive edge clock. Creating register for signal `\top.\sq_figure[9]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$719' with positive edge clock. Creating register for signal `\top.\sq_figure[10]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$720' with positive edge clock. Creating register for signal `\top.\sq_figure[11]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$721' with positive edge clock. Creating register for signal `\top.\sq_figure[12]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$722' with positive edge clock. Creating register for signal `\top.\sq_figure[13]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$723' with positive edge clock. Creating register for signal `\top.\sq_figure[14]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$724' with positive edge clock. Creating register for signal `\top.\sq_figure[15]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$725' with positive edge clock. Creating register for signal `\top.\sq_figure[16]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$726' with positive edge clock. Creating register for signal `\top.\sq_figure[17]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$727' with positive edge clock. Creating register for signal `\top.\sq_figure[18]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$728' with positive edge clock. Creating register for signal `\top.\sq_figure[19]' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$729' with positive edge clock. Creating register for signal `\top.$mem2reg_rd$\sq_figure$example.v:202$6_ADDR' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$730' with positive edge clock. Creating register for signal `\top.$mem2reg_rd$\sq_figure$example.v:202$6_DATA' using process `\top.$proc$example.v:110$16'. created $dff cell `$procdff$731' with positive edge clock. Creating register for signal `\top.\clk_div' using process `\top.$proc$example.v:46$7'. created $dff cell `$procdff$732' with positive edge clock. 2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$proc$example.v:96$109'. Removing empty process `top.$proc$example.v:95$108'. Removing empty process `top.$proc$example.v:94$107'. Removing empty process `top.$proc$example.v:93$106'. Removing empty process `top.$proc$example.v:63$105'. Removing empty process `top.$proc$example.v:62$104'. Found and cleaned up 35 empty switches in `\top.$proc$example.v:110$16'. Removing empty process `top.$proc$example.v:110$16'. Removing empty process `top.$proc$example.v:46$7'. Cleaned up 35 empty switches. 2.4. Executing FLATTEN pass (flatten design). No more expansions possible. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 35 unused cells and 331 unused wires. 2.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 2 cells. 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $procmux$457: \l_arr -> 1'0 Replacing known input bits on port B of cell $procmux$455: \l_arr -> 1'1 Replacing known input bits on port A of cell $procmux$492: \u_arr -> 1'0 Replacing known input bits on port B of cell $procmux$490: \u_arr -> 1'1 Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 2 cells. 2.10.6. Executing OPT_RMDFF pass (remove dff with constant values). Removing $procdff$681 ($dff) from module top. Removing $procdff$710 ($dff) from module top. Removing $procdff$711 ($dff) from module top. Removing $procdff$712 ($dff) from module top. Removing $procdff$713 ($dff) from module top. Removing $procdff$714 ($dff) from module top. Removing $procdff$715 ($dff) from module top. Removing $procdff$716 ($dff) from module top. Removing $procdff$717 ($dff) from module top. Removing $procdff$722 ($dff) from module top. Removing $procdff$723 ($dff) from module top. Removing $procdff$724 ($dff) from module top. Removing $procdff$725 ($dff) from module top. Removing $procdff$726 ($dff) from module top. Removing $procdff$727 ($dff) from module top. Removing $procdff$728 ($dff) from module top. Removing $procdff$729 ($dff) from module top. Replaced 17 DFF cells. 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 16 unused cells and 20 unused wires. 2.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $procmux$537: { $procmux$557_CMP $procmux$549_CMP $procmux$548_CMP $procmux$547_CMP $procmux$546_CMP $procmux$545_CMP $auto$opt_reduce.cc:132:opt_mux$742 $auto$opt_reduce.cc:132:opt_mux$740 $auto$opt_reduce.cc:132:opt_mux$738 $auto$opt_reduce.cc:132:opt_mux$736 $auto$opt_reduce.cc:132:opt_mux$734 } New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$733: { $procmux$538_CMP $procmux$556_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$735: { $procmux$539_CMP $procmux$555_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$737: { $procmux$540_CMP $procmux$554_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$739: { $procmux$541_CMP $procmux$542_CMP $procmux$552_CMP $procmux$553_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$741: { $procmux$543_CMP $procmux$544_CMP $procmux$550_CMP $procmux$551_CMP } Optimizing cells in module \top. Performed a total of 6 changes. 2.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.16. Rerunning OPT passes. (Maybe there is more to do..) 2.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.20. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.23. Finished OPT passes. (There is nothing left to do.) 2.11. Executing WREDUCE pass (reducing word size of cells). Removed top 28 bits (of 32) from port B of cell top.$sub$example.v:79$9 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:79$9 ($sub). Removed top 1 bits (of 2) from port B of cell top.$add$example.v:47$8 ($add). Removed top 28 bits (of 32) from port B of cell top.$add$example.v:80$10 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:80$10 ($add). Removed top 28 bits (of 32) from port B of cell top.$sub$example.v:81$11 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:81$11 ($sub). Removed top 28 bits (of 32) from port B of cell top.$add$example.v:82$12 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:82$12 ($add). Removed top 5 bits (of 10) from port Y of cell top.$sub$example.v:105$13 ($sub). Removed top 5 bits (of 10) from port A of cell top.$sub$example.v:105$13 ($sub). Removed top 5 bits (of 10) from port B of cell top.$sub$example.v:105$13 ($sub). Removed top 5 bits (of 10) from port Y of cell top.$sub$example.v:106$14 ($sub). Removed top 5 bits (of 10) from port A of cell top.$sub$example.v:106$14 ($sub). Removed top 5 bits (of 10) from port B of cell top.$sub$example.v:106$14 ($sub). Removed top 1 bits (of 2) from port B of cell top.$eq$example.v:108$15 ($eq). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:155$27 ($lt). Removed top 24 bits (of 32) from port B of cell top.$gt$example.v:112$24 ($gt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:117$25 ($add). Removed top 24 bits (of 32) from port Y of cell top.$add$example.v:117$25 ($add). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:156$28 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:156$28 ($add). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:160$29 ($lt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:161$30 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:161$30 ($add). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:168$31 ($lt). Removed top 22 bits (of 32) from port B of cell top.$gt$example.v:168$32 ($gt). Removed top 23 bits (of 32) from port B of cell top.$lt$example.v:174$34 ($lt). Removed top 23 bits (of 32) from port B of cell top.$gt$example.v:174$35 ($gt). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:180$37 ($lt). Removed top 23 bits (of 32) from port B of cell top.$lt$example.v:183$38 ($lt). Removed top 1 bits (of 10) from port B of cell top.$eq$example.v:193$51 ($eq). Removed top 9 bits (of 10) from port B of cell top.$eq$example.v:225$71 ($eq). Removed top 9 bits (of 10) from port B of cell top.$eq$example.v:225$72 ($eq). Removed top 28 bits (of 32) from port B of cell top.$gt$example.v:227$74 ($gt). Removed top 31 bits (of 32) from port B of cell top.$sub$example.v:228$75 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:228$75 ($sub). Removed top 23 bits (of 32) from port B of cell top.$lt$example.v:237$76 ($lt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:238$77 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:238$77 ($add). Removed top 28 bits (of 32) from port B of cell top.$gt$example.v:247$78 ($gt). Removed top 31 bits (of 32) from port B of cell top.$sub$example.v:248$79 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:248$79 ($sub). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:257$80 ($lt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:258$81 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:258$81 ($add). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:270$83 ($add). Removed top 28 bits (of 32) from port Y of cell top.$add$example.v:270$83 ($add). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:302$85 ($add). Removed top 11 bits (of 32) from port Y of cell top.$add$example.v:302$85 ($add). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:306$91 ($xor). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:307$92 ($xor). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:308$93 ($xor). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:309$94 ($xor). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:313$96 ($eq). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:326$98 ($eq). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:339$100 ($eq). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:352$102 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$542_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$543_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$544_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$545_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$546_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$547_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$548_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$procmux$549_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$procmux$550_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$procmux$551_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$procmux$552_CMP0 ($eq). Removed top 2 bits (of 5) from port B of cell top.$procmux$553_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$procmux$554_CMP0 ($eq). Removed top 3 bits (of 5) from port B of cell top.$procmux$555_CMP0 ($eq). Removed top 4 bits (of 5) from port B of cell top.$procmux$556_CMP0 ($eq). Removed cell top.$procmux$558 ($mux). Removed cell top.$procmux$561 ($mux). Removed cell top.$procmux$563 ($mux). Removed top 24 bits (of 32) from wire top.$add$example.v:117$25_Y. Removed top 22 bits (of 32) from wire top.$add$example.v:161$30_Y. Removed top 22 bits (of 32) from wire top.$add$example.v:258$81_Y. Removed top 22 bits (of 32) from wire top.$sub$example.v:228$75_Y. Removed top 22 bits (of 32) from wire top.$sub$example.v:248$79_Y. 2.12. Executing PEEPOPT pass (run peephole optimizers). 2.13. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 15 unused wires. 2.14. Executing SHARE pass (SAT-based resource sharing). 2.15. Executing TECHMAP pass (map to technology primitives). 2.15.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.15.2. Continuing TECHMAP pass. Using template $paramod$6816abac91a51b405c3de5bceb2855c03dd44485\_90_lut_cmp_ for cells of type $eq. Using template $paramod$dc6060208f0369ff43b26b7eee8e43bf61e4b025\_90_lut_cmp_ for cells of type $eq. No more expansions possible. 2.16. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 6 unused wires. 2.18. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $add$example.v:117$25 ($add). creating $macc model for $add$example.v:156$28 ($add). creating $macc model for $add$example.v:161$30 ($add). creating $macc model for $add$example.v:238$77 ($add). creating $macc model for $add$example.v:258$81 ($add). creating $macc model for $add$example.v:270$83 ($add). creating $macc model for $add$example.v:302$85 ($add). creating $macc model for $add$example.v:47$8 ($add). creating $macc model for $add$example.v:80$10 ($add). creating $macc model for $add$example.v:82$12 ($add). creating $macc model for $sub$example.v:105$13 ($sub). creating $macc model for $sub$example.v:106$14 ($sub). creating $macc model for $sub$example.v:228$75 ($sub). creating $macc model for $sub$example.v:248$79 ($sub). creating $macc model for $sub$example.v:79$9 ($sub). creating $macc model for $sub$example.v:81$11 ($sub). creating $alu model for $macc $sub$example.v:81$11. creating $alu model for $macc $sub$example.v:79$9. creating $alu model for $macc $sub$example.v:248$79. creating $alu model for $macc $sub$example.v:228$75. creating $alu model for $macc $sub$example.v:106$14. creating $alu model for $macc $sub$example.v:105$13. creating $alu model for $macc $add$example.v:82$12. creating $alu model for $macc $add$example.v:80$10. creating $alu model for $macc $add$example.v:47$8. creating $alu model for $macc $add$example.v:302$85. creating $alu model for $macc $add$example.v:270$83. creating $alu model for $macc $add$example.v:258$81. creating $alu model for $macc $add$example.v:238$77. creating $alu model for $macc $add$example.v:161$30. creating $alu model for $macc $add$example.v:156$28. creating $alu model for $macc $add$example.v:117$25. creating $alu model for $gt$example.v:112$24 ($gt): new $alu creating $alu model for $gt$example.v:168$32 ($gt): new $alu creating $alu model for $gt$example.v:174$35 ($gt): new $alu creating $alu model for $gt$example.v:198$58 ($gt): new $alu creating $alu model for $gt$example.v:198$61 ($gt): new $alu creating $alu model for $gt$example.v:227$74 ($gt): new $alu creating $alu model for $gt$example.v:247$78 ($gt): new $alu creating $alu model for $lt$example.v:155$27 ($lt): new $alu creating $alu model for $lt$example.v:160$29 ($lt): new $alu creating $alu model for $lt$example.v:168$31 ($lt): new $alu creating $alu model for $lt$example.v:174$34 ($lt): new $alu creating $alu model for $lt$example.v:180$37 ($lt): new $alu creating $alu model for $lt$example.v:183$38 ($lt): new $alu creating $alu model for $lt$example.v:198$59 ($lt): new $alu creating $alu model for $lt$example.v:198$63 ($lt): new $alu creating $alu model for $lt$example.v:237$76 ($lt): new $alu creating $alu model for $lt$example.v:257$80 ($lt): new $alu creating $alu cell for $lt$example.v:257$80: $auto$alumacc.cc:474:replace_alu$769 creating $alu cell for $lt$example.v:237$76: $auto$alumacc.cc:474:replace_alu$774 creating $alu cell for $lt$example.v:198$63: $auto$alumacc.cc:474:replace_alu$785 creating $alu cell for $lt$example.v:198$59: $auto$alumacc.cc:474:replace_alu$790 creating $alu cell for $lt$example.v:183$38: $auto$alumacc.cc:474:replace_alu$795 creating $alu cell for $lt$example.v:180$37: $auto$alumacc.cc:474:replace_alu$806 creating $alu cell for $lt$example.v:174$34: $auto$alumacc.cc:474:replace_alu$811 creating $alu cell for $lt$example.v:168$31: $auto$alumacc.cc:474:replace_alu$822 creating $alu cell for $lt$example.v:160$29: $auto$alumacc.cc:474:replace_alu$827 creating $alu cell for $lt$example.v:155$27: $auto$alumacc.cc:474:replace_alu$832 creating $alu cell for $gt$example.v:198$61: $auto$alumacc.cc:474:replace_alu$843 creating $alu cell for $gt$example.v:198$58: $auto$alumacc.cc:474:replace_alu$854 creating $alu cell for $gt$example.v:174$35: $auto$alumacc.cc:474:replace_alu$859 creating $alu cell for $gt$example.v:168$32: $auto$alumacc.cc:474:replace_alu$864 creating $alu cell for $gt$example.v:112$24: $auto$alumacc.cc:474:replace_alu$875 creating $alu cell for $add$example.v:117$25: $auto$alumacc.cc:474:replace_alu$886 creating $alu cell for $add$example.v:156$28: $auto$alumacc.cc:474:replace_alu$889 creating $alu cell for $add$example.v:161$30: $auto$alumacc.cc:474:replace_alu$892 creating $alu cell for $add$example.v:238$77: $auto$alumacc.cc:474:replace_alu$895 creating $alu cell for $add$example.v:258$81: $auto$alumacc.cc:474:replace_alu$898 creating $alu cell for $add$example.v:270$83: $auto$alumacc.cc:474:replace_alu$901 creating $alu cell for $add$example.v:302$85: $auto$alumacc.cc:474:replace_alu$904 creating $alu cell for $add$example.v:47$8: $auto$alumacc.cc:474:replace_alu$907 creating $alu cell for $gt$example.v:247$78: $auto$alumacc.cc:474:replace_alu$910 creating $alu cell for $add$example.v:80$10: $auto$alumacc.cc:474:replace_alu$915 creating $alu cell for $gt$example.v:227$74: $auto$alumacc.cc:474:replace_alu$918 creating $alu cell for $add$example.v:82$12: $auto$alumacc.cc:474:replace_alu$923 creating $alu cell for $sub$example.v:105$13: $auto$alumacc.cc:474:replace_alu$926 creating $alu cell for $sub$example.v:106$14: $auto$alumacc.cc:474:replace_alu$929 creating $alu cell for $sub$example.v:228$75: $auto$alumacc.cc:474:replace_alu$932 creating $alu cell for $sub$example.v:248$79: $auto$alumacc.cc:474:replace_alu$935 creating $alu cell for $sub$example.v:79$9: $auto$alumacc.cc:474:replace_alu$938 creating $alu cell for $sub$example.v:81$11: $auto$alumacc.cc:474:replace_alu$941 created 33 $alu and 0 $macc cells. 2.19. Executing OPT pass (performing simple optimizations). 2.19.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$777: { $auto$alumacc.cc:490:replace_alu$775 [0] $auto$alumacc.cc:490:replace_alu$775 [1] $auto$alumacc.cc:490:replace_alu$775 [2] $auto$alumacc.cc:490:replace_alu$775 [3] $auto$alumacc.cc:490:replace_alu$775 [4] $auto$alumacc.cc:490:replace_alu$775 [5] $auto$alumacc.cc:490:replace_alu$775 [6] $auto$alumacc.cc:490:replace_alu$775 [7] $auto$alumacc.cc:490:replace_alu$775 [8] $auto$alumacc.cc:490:replace_alu$775 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$798: { $auto$alumacc.cc:490:replace_alu$796 [0] $auto$alumacc.cc:490:replace_alu$796 [1] $auto$alumacc.cc:490:replace_alu$796 [2] $auto$alumacc.cc:490:replace_alu$796 [3] $auto$alumacc.cc:490:replace_alu$796 [4] $auto$alumacc.cc:490:replace_alu$796 [5] $auto$alumacc.cc:490:replace_alu$796 [6] $auto$alumacc.cc:490:replace_alu$796 [7] $auto$alumacc.cc:490:replace_alu$796 [8] $auto$alumacc.cc:490:replace_alu$796 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$814: { $auto$alumacc.cc:490:replace_alu$812 [0] $auto$alumacc.cc:490:replace_alu$812 [1] $auto$alumacc.cc:490:replace_alu$812 [2] $auto$alumacc.cc:490:replace_alu$812 [3] $auto$alumacc.cc:490:replace_alu$812 [4] $auto$alumacc.cc:490:replace_alu$812 [5] $auto$alumacc.cc:490:replace_alu$812 [6] $auto$alumacc.cc:490:replace_alu$812 [7] $auto$alumacc.cc:490:replace_alu$812 [8] $auto$alumacc.cc:490:replace_alu$812 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$835: { $auto$alumacc.cc:490:replace_alu$833 [0] $auto$alumacc.cc:490:replace_alu$833 [1] $auto$alumacc.cc:490:replace_alu$833 [2] $auto$alumacc.cc:490:replace_alu$833 [3] $auto$alumacc.cc:490:replace_alu$833 [4] $auto$alumacc.cc:490:replace_alu$833 [5] $auto$alumacc.cc:490:replace_alu$833 [6] $auto$alumacc.cc:490:replace_alu$833 [7] $auto$alumacc.cc:490:replace_alu$833 [8] $auto$alumacc.cc:490:replace_alu$833 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$846: { $auto$alumacc.cc:490:replace_alu$844 [0] $auto$alumacc.cc:490:replace_alu$844 [1] $auto$alumacc.cc:490:replace_alu$844 [2] $auto$alumacc.cc:490:replace_alu$844 [3] $auto$alumacc.cc:490:replace_alu$844 [4] $auto$alumacc.cc:490:replace_alu$844 [5] $auto$alumacc.cc:490:replace_alu$844 [6] $auto$alumacc.cc:490:replace_alu$844 [7] $auto$alumacc.cc:490:replace_alu$844 [8] $auto$alumacc.cc:490:replace_alu$844 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$867: { $auto$alumacc.cc:490:replace_alu$865 [0] $auto$alumacc.cc:490:replace_alu$865 [1] $auto$alumacc.cc:490:replace_alu$865 [2] $auto$alumacc.cc:490:replace_alu$865 [3] $auto$alumacc.cc:490:replace_alu$865 [4] $auto$alumacc.cc:490:replace_alu$865 [5] $auto$alumacc.cc:490:replace_alu$865 [6] $auto$alumacc.cc:490:replace_alu$865 [7] $auto$alumacc.cc:490:replace_alu$865 [8] $auto$alumacc.cc:490:replace_alu$865 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$878: { $auto$alumacc.cc:490:replace_alu$876 [0] $auto$alumacc.cc:490:replace_alu$876 [1] $auto$alumacc.cc:490:replace_alu$876 [2] $auto$alumacc.cc:490:replace_alu$876 [3] $auto$alumacc.cc:490:replace_alu$876 [4] $auto$alumacc.cc:490:replace_alu$876 [5] $auto$alumacc.cc:490:replace_alu$876 [6] $auto$alumacc.cc:490:replace_alu$876 [7] } Optimizing cells in module \top. Performed a total of 7 changes. 2.19.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.19.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.19.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 7 unused cells and 24 unused wires. 2.19.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19.9. Rerunning OPT passes. (Maybe there is more to do..) 2.19.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.19.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.19.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.19.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.19.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.19.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19.16. Finished OPT passes. (There is nothing left to do.) 2.20. Executing FSM pass (extract and optimize FSM). 2.20.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.vga_b_r as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. Not marking top.vga_r_r as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. 2.20.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.20.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.20.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.20.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.20.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.20.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.20.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.21. Executing OPT pass (performing simple optimizations). 2.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.21.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.21.5. Finished fast OPT passes. 2.22. Executing MEMORY pass. 2.22.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 2.22.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.22.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.22.5. Executing MEMORY_COLLECT pass (generating $mem cells). 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). 2.25. Executing TECHMAP pass (map to technology primitives). 2.25.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 2.25.2. Continuing TECHMAP pass. No more expansions possible. 2.26. Executing ICE40_BRAMINIT pass. 2.27. Executing OPT pass (performing simple optimizations). 2.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.27.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 4 unused wires. 2.27.5. Finished fast OPT passes. 2.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 2.29. Executing OPT pass (performing simple optimizations). 2.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$651: Old ports: A=3'000, B=3'111, Y=$procmux$651_Y New ports: A=1'0, B=1'1, Y=$procmux$651_Y [0] New connections: $procmux$651_Y [2:1] = { $procmux$651_Y [0] $procmux$651_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$653: Old ports: A=3'000, B=$procmux$651_Y, Y=$procmux$653_Y New ports: A=1'0, B=$procmux$651_Y [0], Y=$procmux$653_Y [0] New connections: $procmux$653_Y [2:1] = { $procmux$653_Y [0] $procmux$653_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$656: Old ports: A=$procmux$653_Y, B=3'000, Y=$procmux$656_Y New ports: A=$procmux$653_Y [0], B=1'0, Y=$procmux$656_Y [0] New connections: $procmux$656_Y [2:1] = { $procmux$656_Y [0] $procmux$656_Y [0] } Consolidated identical input bits for $mux cell $procmux$676: Old ports: A=$procmux$653_Y, B=3'111, Y=$procmux$676_Y New ports: A=$procmux$653_Y [0], B=1'1, Y=$procmux$676_Y [0] New connections: $procmux$676_Y [2:1] = { $procmux$676_Y [0] $procmux$676_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$658: Old ports: A=3'000, B=$procmux$656_Y, Y=$0\vga_b_r[2:0] New ports: A=1'0, B=$procmux$656_Y [0], Y=$0\vga_b_r[2:0] [0] New connections: $0\vga_b_r[2:0] [2:1] = { $0\vga_b_r[2:0] [0] $0\vga_b_r[2:0] [0] } Consolidated identical input bits for $mux cell $procmux$678: Old ports: A=3'000, B=$procmux$676_Y, Y=$0\vga_r_r[2:0] New ports: A=1'0, B=$procmux$676_Y [0], Y=$0\vga_r_r[2:0] [0] New connections: $0\vga_r_r[2:0] [2:1] = { $0\vga_r_r[2:0] [0] $0\vga_r_r[2:0] [0] } Optimizing cells in module \top. Performed a total of 6 changes. 2.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.9. Rerunning OPT passes. (Maybe there is more to do..) 2.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.16. Finished OPT passes. (There is nothing left to do.) 2.30. Executing TECHMAP pass (map to technology primitives). 2.30.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.30.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.30.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=4\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=20\S_WIDTH=10 for cells of type $pmux. Using template $paramod$constmap:2b38e406732613cd884da597c99291ccae15b378$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx for cells of type $shiftx. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $mux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=1\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=21\Y_WIDTH=21 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $and. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. No more expansions possible. 2.31. Executing ICE40_OPT pass (performing simple optimizations). 2.31.1. Running ICE40 specific optimizations. 2.31.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 298 cells. 2.31.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 352 unused cells and 732 unused wires. 2.31.6. Rerunning OPT passes. (Removed registers in this run.) 2.31.7. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$769.slice[0].carry: CO=\sq_pos_x [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$774.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$795.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$795.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$811.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$795.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$822.slice[0].carry: CO=\c_hor [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$827.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$832.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$859.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$795.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$864.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$875.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$886.slice[0].carry: CO=\timer_t [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$889.slice[0].carry: CO=\c_hor [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$892.slice[0].carry: CO=\c_ver [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$895.slice[0].carry: CO=\sq_pos_y [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$898.slice[0].carry: CO=\sq_pos_x [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$901.slice[0].carry: CO=\ps2_cntr [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$904.slice[0].carry: CO=\arr_timer [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$910.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$910.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$915.slice[0].carry: CO=1'0 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$918.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$774.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$923.slice[0].carry: CO=1'0 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$932.slice[0].carry: CO=\sq_pos_y [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$935.slice[0].carry: CO=\sq_pos_x [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$938.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$941.slice[0].carry: CO=1'1 Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$886.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$889.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$892.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$895.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$898.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$901.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$904.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$915.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$923.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$932.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$935.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$938.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$941.slice[1].adder back to logic. 2.31.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 14 cells. 2.31.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 47 unused wires. 2.31.12. Rerunning OPT passes. (Removed registers in this run.) 2.31.13. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$774.slice[1].carry: CO=\d_sq_pos_y [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$827.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$832.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$864.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$875.slice[1].carry: CO=\timer_t [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$915.slice[1].carry: CO=\sq_pos_x [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$923.slice[1].carry: CO=\sq_pos_y [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$938.slice[1].carry: CO=\sq_pos_x [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$941.slice[1].carry: CO=\sq_pos_y [1] Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$915.slice[2].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$923.slice[2].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$938.slice[2].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$941.slice[2].adder back to logic. 2.31.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 6 cells. 2.31.16. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 16 unused wires. 2.31.18. Rerunning OPT passes. (Removed registers in this run.) 2.31.19. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[2].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$827.slice[2].carry: CO=\c_ver [2] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$832.slice[2].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$864.slice[2].carry: CO=1'1 2.31.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.22. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.24. Rerunning OPT passes. (Removed registers in this run.) 2.31.25. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[3].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$832.slice[3].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$864.slice[3].carry: CO=1'1 2.31.26. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.27. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.28. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.29. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.30. Rerunning OPT passes. (Removed registers in this run.) 2.31.31. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[4].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$832.slice[4].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$864.slice[4].carry: CO=\c_hor [4] 2.31.32. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.34. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.36. Rerunning OPT passes. (Removed registers in this run.) 2.31.37. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[5].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$832.slice[5].carry: CO=$auto$alumacc.cc:474:replace_alu$832.BB [5] 2.31.38. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.39. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.40. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.41. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.42. Rerunning OPT passes. (Removed registers in this run.) 2.31.43. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[6].carry: CO=1'1 2.31.44. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.45. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.46. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.47. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.48. Rerunning OPT passes. (Removed registers in this run.) 2.31.49. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$806.slice[7].carry: CO=\c_hor [7] 2.31.50. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.51. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.52. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.53. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.54. Rerunning OPT passes. (Removed registers in this run.) 2.31.55. Running ICE40 specific optimizations. 2.31.56. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.31.57. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.31.58. Executing OPT_RMDFF pass (remove dff with constant values). 2.31.59. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.31.60. Finished OPT passes. (There is nothing left to do.) 2.32. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). 2.33. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). Selected cell types for direct conversion: $_DFF_PP1_ -> $__DFFE_PP1 $_DFF_PP0_ -> $__DFFE_PP0 $_DFF_PN1_ -> $__DFFE_PN1 $_DFF_PN0_ -> $__DFFE_PN0 $_DFF_NP1_ -> $__DFFE_NP1 $_DFF_NP0_ -> $__DFFE_NP0 $_DFF_NN1_ -> $__DFFE_NN1 $_DFF_NN0_ -> $__DFFE_NN0 $_DFF_N_ -> $_DFFE_NP_ $_DFF_P_ -> $_DFFE_PP_ Transforming FF to FF+Enable cells in module top: converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2528 to $_DFFE_PP_ for $0\timer_t[7:0] [0] -> \timer_t [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2529 to $_DFFE_PP_ for $0\timer_t[7:0] [1] -> \timer_t [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2530 to $_DFFE_PP_ for $0\timer_t[7:0] [2] -> \timer_t [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2531 to $_DFFE_PP_ for $0\timer_t[7:0] [3] -> \timer_t [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2532 to $_DFFE_PP_ for $0\timer_t[7:0] [4] -> \timer_t [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2533 to $_DFFE_PP_ for $0\timer_t[7:0] [5] -> \timer_t [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2534 to $_DFFE_PP_ for $0\timer_t[7:0] [6] -> \timer_t [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2535 to $_DFFE_PP_ for $0\timer_t[7:0] [7] -> \timer_t [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2537 to $_DFFE_PP_ for $0\c_row[9:0] [0] -> \c_row [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2538 to $_DFFE_PP_ for $0\c_row[9:0] [1] -> \c_row [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2539 to $_DFFE_PP_ for $0\c_row[9:0] [2] -> \c_row [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2540 to $_DFFE_PP_ for $0\c_row[9:0] [3] -> \c_row [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2541 to $_DFFE_PP_ for $0\c_row[9:0] [4] -> \c_row [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2542 to $_DFFE_PP_ for $0\c_row[9:0] [5] -> \c_row [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2543 to $_DFFE_PP_ for $0\c_row[9:0] [6] -> \c_row [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2544 to $_DFFE_PP_ for $0\c_row[9:0] [7] -> \c_row [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2545 to $_DFFE_PP_ for $0\c_row[9:0] [8] -> \c_row [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2546 to $_DFFE_PP_ for $0\c_row[9:0] [9] -> \c_row [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2547 to $_DFFE_PP_ for $0\c_col[9:0] [0] -> \c_col [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2548 to $_DFFE_PP_ for $0\c_col[9:0] [1] -> \c_col [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2549 to $_DFFE_PP_ for $0\c_col[9:0] [2] -> \c_col [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2550 to $_DFFE_PP_ for $0\c_col[9:0] [3] -> \c_col [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2551 to $_DFFE_PP_ for $0\c_col[9:0] [4] -> \c_col [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2552 to $_DFFE_PP_ for $0\c_col[9:0] [5] -> \c_col [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2553 to $_DFFE_PP_ for $0\c_col[9:0] [6] -> \c_col [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2554 to $_DFFE_PP_ for $0\c_col[9:0] [7] -> \c_col [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2555 to $_DFFE_PP_ for $0\c_col[9:0] [8] -> \c_col [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2556 to $_DFFE_PP_ for $0\c_col[9:0] [9] -> \c_col [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2558 to $_DFFE_PP_ for $0\c_hor[9:0] [1] -> \c_hor [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2567 to $_DFFE_PP_ for $0\c_ver[9:0] [0] -> \c_ver [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2568 to $_DFFE_PP_ for $0\c_ver[9:0] [1] -> \c_ver [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2569 to $_DFFE_PP_ for $0\c_ver[9:0] [2] -> \c_ver [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2570 to $_DFFE_PP_ for $0\c_ver[9:0] [3] -> \c_ver [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2571 to $_DFFE_PP_ for $0\c_ver[9:0] [4] -> \c_ver [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2572 to $_DFFE_PP_ for $0\c_ver[9:0] [5] -> \c_ver [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2573 to $_DFFE_PP_ for $0\c_ver[9:0] [6] -> \c_ver [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2574 to $_DFFE_PP_ for $0\c_ver[9:0] [7] -> \c_ver [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2575 to $_DFFE_PP_ for $0\c_ver[9:0] [8] -> \c_ver [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2576 to $_DFFE_PP_ for $0\c_ver[9:0] [9] -> \c_ver [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2579 to $_DFFE_PP_ for $0\sq_pos_x[9:0] [1] -> \sq_pos_x [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2589 to $_DFFE_PP_ for $0\sq_pos_y[9:0] [1] -> \sq_pos_y [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2598 to $_DFFE_PP_ for $0\ps2_cntr[3:0] [0] -> \ps2_cntr [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2599 to $_DFFE_PP_ for $0\ps2_cntr[3:0] [1] -> \ps2_cntr [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2600 to $_DFFE_PP_ for $0\ps2_cntr[3:0] [2] -> \ps2_cntr [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2601 to $_DFFE_PP_ for $0\ps2_cntr[3:0] [3] -> \ps2_cntr [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2610 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [0] -> \ps2_data_reg_prev [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2611 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [1] -> \ps2_data_reg_prev [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2612 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [2] -> \ps2_data_reg_prev [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2613 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [3] -> \ps2_data_reg_prev [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2614 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [4] -> \ps2_data_reg_prev [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2615 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [5] -> \ps2_data_reg_prev [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2616 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [6] -> \ps2_data_reg_prev [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2617 to $_DFFE_PP_ for $0\ps2_data_reg_prev[7:0] [7] -> \ps2_data_reg_prev [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2618 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [0] -> \ps2_dat_r [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2619 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [1] -> \ps2_dat_r [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2620 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [2] -> \ps2_dat_r [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2621 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [3] -> \ps2_dat_r [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2622 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [4] -> \ps2_dat_r [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2623 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [5] -> \ps2_dat_r [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2624 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [6] -> \ps2_dat_r [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2625 to $_DFFE_PP_ for $0\ps2_dat_r[10:0] [7] -> \ps2_dat_r [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2636 to $_DFFE_PP_ for $0\arr_timer[20:0] [1] -> \arr_timer [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2657 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [0] -> \sq_figure[8] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2658 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [1] -> \sq_figure[8] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2659 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [2] -> \sq_figure[8] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2660 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [3] -> \sq_figure[8] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2661 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [4] -> \sq_figure[8] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2662 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [5] -> \sq_figure[8] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2663 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [6] -> \sq_figure[8] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2664 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [7] -> \sq_figure[8] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2665 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [8] -> \sq_figure[8] [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2666 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [9] -> \sq_figure[8] [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2667 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [10] -> \sq_figure[8] [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2668 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [11] -> \sq_figure[8] [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2669 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [12] -> \sq_figure[8] [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2670 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [13] -> \sq_figure[8] [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2671 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [14] -> \sq_figure[8] [14]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2672 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [15] -> \sq_figure[8] [15]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2673 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [16] -> \sq_figure[8] [16]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2674 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [17] -> \sq_figure[8] [17]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2675 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [18] -> \sq_figure[8] [18]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2676 to $_DFFE_PP_ for $0\sq_figure[8][19:0] [19] -> \sq_figure[8] [19]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2677 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [0] -> \sq_figure[9] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2678 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [1] -> \sq_figure[9] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2679 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [2] -> \sq_figure[9] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2680 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [3] -> \sq_figure[9] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2681 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [4] -> \sq_figure[9] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2682 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [5] -> \sq_figure[9] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2683 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [6] -> \sq_figure[9] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2684 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [7] -> \sq_figure[9] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2685 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [8] -> \sq_figure[9] [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2686 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [9] -> \sq_figure[9] [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2687 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [10] -> \sq_figure[9] [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2688 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [11] -> \sq_figure[9] [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2689 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [12] -> \sq_figure[9] [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2690 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [13] -> \sq_figure[9] [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2691 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [14] -> \sq_figure[9] [14]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2692 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [15] -> \sq_figure[9] [15]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2693 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [16] -> \sq_figure[9] [16]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2694 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [17] -> \sq_figure[9] [17]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2695 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [18] -> \sq_figure[9] [18]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2696 to $_DFFE_PP_ for $0\sq_figure[9][19:0] [19] -> \sq_figure[9] [19]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2697 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [0] -> \sq_figure[10] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2698 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [1] -> \sq_figure[10] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2699 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [2] -> \sq_figure[10] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2700 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [3] -> \sq_figure[10] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2701 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [4] -> \sq_figure[10] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2702 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [5] -> \sq_figure[10] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2703 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [6] -> \sq_figure[10] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2704 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [7] -> \sq_figure[10] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2705 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [8] -> \sq_figure[10] [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2706 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [9] -> \sq_figure[10] [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2707 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [10] -> \sq_figure[10] [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2708 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [11] -> \sq_figure[10] [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2709 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [12] -> \sq_figure[10] [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2710 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [13] -> \sq_figure[10] [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2711 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [14] -> \sq_figure[10] [14]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2712 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [15] -> \sq_figure[10] [15]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2713 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [16] -> \sq_figure[10] [16]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2714 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [17] -> \sq_figure[10] [17]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2715 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [18] -> \sq_figure[10] [18]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2716 to $_DFFE_PP_ for $0\sq_figure[10][19:0] [19] -> \sq_figure[10] [19]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2717 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [0] -> \sq_figure[11] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2718 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [1] -> \sq_figure[11] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2719 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [2] -> \sq_figure[11] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2720 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [3] -> \sq_figure[11] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2721 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [4] -> \sq_figure[11] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2722 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [5] -> \sq_figure[11] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2723 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [6] -> \sq_figure[11] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2724 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [7] -> \sq_figure[11] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2725 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [8] -> \sq_figure[11] [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2726 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [9] -> \sq_figure[11] [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2727 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [10] -> \sq_figure[11] [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2728 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [11] -> \sq_figure[11] [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2729 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [12] -> \sq_figure[11] [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2730 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [13] -> \sq_figure[11] [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2731 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [14] -> \sq_figure[11] [14]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2732 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [15] -> \sq_figure[11] [15]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2733 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [16] -> \sq_figure[11] [16]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2734 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [17] -> \sq_figure[11] [17]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2735 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [18] -> \sq_figure[11] [18]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2736 to $_DFFE_PP_ for $0\sq_figure[11][19:0] [19] -> \sq_figure[11] [19]. 2.34. Executing TECHMAP pass (map to technology primitives). 2.34.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Successfully finished Verilog frontend. 2.34.2. Continuing TECHMAP pass. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. No more expansions possible. 2.35. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.36. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.37. Executing ICE40_FFINIT pass (implement FF init values). Handling FF init values in top. FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2534 (SB_DFFE): \timer_t [6] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2529 (SB_DFFE): \timer_t [1] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2530 (SB_DFFE): \timer_t [2] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2531 (SB_DFFE): \timer_t [3] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2532 (SB_DFFE): \timer_t [4] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2533 (SB_DFFE): \timer_t [5] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2535 (SB_DFFE): \timer_t [7] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2536 (SB_DFF): \reset = 1 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2528 (SB_DFFE): \timer_t [0] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2631 (SB_DFF): \u_arr = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2632 (SB_DFF): \l_arr = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2633 (SB_DFF): \d_arr = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$2634 (SB_DFF): \r_arr = 0 2.38. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells). Merging set/reset $_MUX_ cells into SB_FFs in top. Merging $auto$simplemap.cc:277:simplemap_mux$2519 (A=1'0, B=$procmux$676_Y [2], S=$logic_and$example.v:192$44_Y) into $auto$simplemap.cc:420:simplemap_dff$2521 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2496 (A=1'0, B=$procmux$656_Y [2], S=$logic_and$example.v:192$44_Y) into $auto$simplemap.cc:420:simplemap_dff$2524 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2446 (A=\c_ver [7], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2544 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2440 (A=\c_ver [1], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2538 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2441 (A=\c_ver [2], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2539 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2442 (A=\c_ver [3], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2540 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2443 (A=\c_ver [4], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2541 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2444 (A=\c_ver [5], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2542 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2445 (A=\c_ver [6], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2543 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2447 (A=\c_ver [8], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2545 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2448 (A=\c_ver [9], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2546 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2450 (A=\c_hor [0], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2547 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2451 (A=\c_hor [1], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2548 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2452 (A=\c_hor [2], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2549 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2453 (A=\c_hor [3], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2550 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2454 (A=\c_hor [4], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2551 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2455 (A=\c_hor [5], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2552 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2456 (A=\c_hor [6], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2553 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2439 (A=\c_ver [0], B=1'0, S=$auto$rtlil.cc:1836:Or$803) into $auto$simplemap.cc:420:simplemap_dff$2537 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2457 (A=\c_hor [7], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2554 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2459 (A=\c_hor [9], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2556 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2429 (A=$procmux$615_Y [0], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2557 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2430 (A=$procmux$615_Y [1], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2558 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2431 (A=$procmux$615_Y [2], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2559 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2432 (A=$procmux$615_Y [3], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2560 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2433 (A=$procmux$615_Y [4], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2561 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2434 (A=$procmux$615_Y [5], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2562 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2435 (A=$procmux$615_Y [6], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2563 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2458 (A=\c_hor [8], B=1'0, S=$auto$alumacc.cc:491:replace_alu$808 [9]) into $auto$simplemap.cc:420:simplemap_dff$2555 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2436 (A=$procmux$615_Y [7], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2564 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2438 (A=$procmux$615_Y [9], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2566 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2398 (A=$procmux$606_Y [0], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2567 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2399 (A=$procmux$606_Y [1], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2568 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2400 (A=$procmux$606_Y [2], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2569 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2401 (A=$procmux$606_Y [3], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2570 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2402 (A=$procmux$606_Y [4], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2571 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2403 (A=$procmux$606_Y [5], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2572 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2404 (A=$procmux$606_Y [6], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2573 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2437 (A=$procmux$615_Y [8], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2565 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$2405 (A=$procmux$606_Y [7], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2574 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2407 (A=$procmux$606_Y [9], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2576 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2406 (A=$procmux$606_Y [8], B=1'0, S=\reset) into $auto$simplemap.cc:420:simplemap_dff$2575 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2242 (A=$add$example.v:270$83_Y [0], B=1'0, S=$auto$simplemap.cc:309:simplemap_lut$2515) into $auto$simplemap.cc:420:simplemap_dff$2598 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2243 (A=$auto$simplemap.cc:309:simplemap_lut$4409 [1], B=1'0, S=$auto$simplemap.cc:309:simplemap_lut$2515) into $auto$simplemap.cc:420:simplemap_dff$2599 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2244 (A=$add$example.v:270$83_Y [2], B=1'0, S=$auto$simplemap.cc:309:simplemap_lut$2515) into $auto$simplemap.cc:420:simplemap_dff$2600 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$2245 (A=$add$example.v:270$83_Y [3], B=1'0, S=$auto$simplemap.cc:309:simplemap_lut$2515) into $auto$simplemap.cc:420:simplemap_dff$2601 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1687 (A=$xor$example.v:306$91_Y [9], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2666 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1688 (A=$xor$example.v:306$91_Y [10], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2667 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1689 (A=$xor$example.v:306$91_Y [11], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2668 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1690 (A=$xor$example.v:306$91_Y [12], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2669 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1707 (A=$xor$example.v:307$92_Y [9], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2686 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1708 (A=$xor$example.v:307$92_Y [10], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2687 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1709 (A=$xor$example.v:307$92_Y [11], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2688 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1710 (A=$xor$example.v:307$92_Y [12], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2689 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1667 (A=$xor$example.v:308$93_Y [9], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2706 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1668 (A=$xor$example.v:308$93_Y [10], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2707 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1669 (A=$xor$example.v:308$93_Y [11], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2708 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1670 (A=$xor$example.v:308$93_Y [12], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2709 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1587 (A=$xor$example.v:309$94_Y [9], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2726 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1588 (A=$xor$example.v:309$94_Y [10], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2727 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1589 (A=$xor$example.v:309$94_Y [11], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2728 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$1590 (A=$xor$example.v:309$94_Y [12], B=1'1, S=$auto$simplemap.cc:168:logic_reduce$1304) into $auto$simplemap.cc:420:simplemap_dff$2729 (SB_DFFE). 2.39. Executing ICE40_OPT pass (performing simple optimizations). 2.39.1. Running ICE40 specific optimizations. 2.39.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 290 cells. 2.39.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 62 unused cells and 1488 unused wires. 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 2.39.7. Running ICE40 specific optimizations. 2.39.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.39.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.39.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 2.39.12. Finished OPT passes. (There is nothing left to do.) 2.40. Executing TECHMAP pass (map to technology primitives). 2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 2.40.2. Continuing TECHMAP pass. No more expansions possible. 2.41. Executing ABC pass (technology mapping using ABC). 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. Extracted 959 gates and 1276 wires to a netlist network with 315 inputs and 175 outputs. 2.41.1.1. Executing ABC. Running ABC command: abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + retime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 212. ABC: Participating nodes from both networks = 474. ABC: Participating nodes from the first network = 215. ( 55.99 % of nodes) ABC: Participating nodes from the second network = 259. ( 67.45 % of nodes) ABC: Node pairs (any polarity) = 215. ( 55.99 % of names can be moved) ABC: Node pairs (same polarity) = 192. ( 50.00 % of names can be moved) ABC: Total runtime = 0.03 sec ABC: + write_blif /output.blif 2.41.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 766 ABC RESULTS: internal signals: 786 ABC RESULTS: input signals: 315 ABC RESULTS: output signals: 175 Removing temp directory. Removed 0 unused cells and 737 unused wires. 2.42. Executing TECHMAP pass (map to technology primitives). 2.42.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.42.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100001110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000100110010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110100001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010111110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010001100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010110000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. No more expansions possible. Removed 0 unused cells and 766 unused wires. 2.43. Executing HIERARCHY pass (managing design hierarchy). 2.43.1. Analyzing design hierarchy.. Top module: \top 2.43.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.44. Printing statistics. === top === Number of wires: 519 Number of wire bits: 1435 Number of public wires: 62 Number of public wire bits: 615 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 966 SB_CARRY 246 SB_DFF 58 SB_DFFE 91 SB_DFFESR 35 SB_DFFESS 16 SB_DFFSR 11 SB_LUT4 509 2.45. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.46. Executing BLIF backend. Warnings: 1 unique messages, 1 total End of script. Logfile hash: fa4f52eace CPU: user 4.87s system 0.04s, MEM: 66.16 MB total, 54.50 MB resident Yosys 0.8+ (git sha1 UNKNOWN, c++ 8.3 -O2 -fno-strict-aliasing -fPIC -Os) Time spent: 23% 29x opt_clean (1 sec), 18% 29x opt_expr (0 sec), ... arachne-pnr -d 8k -o example.asc -p ice40-io-video.pcf example.blif -P ct256 seed: 1 device: 8k read_chipdb +/share/arachne-pnr/chipdb-8k.bin... supported packages: bg121, bg121:4k, cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k read_blif example.blif... prune... read_pcf ice40-io-video.pcf... instantiate_io... pack... After packing: IOs 14 / 206 GBs 0 / 8 GB_IOs 0 / 8 LCs 829 / 7680 DFF 187 CARRY 248 CARRY, DFF 24 DFF PASS 103 CARRY PASS 67 BRAMs 0 / 32 WARMBOOTs 0 / 1 PLLs 0 / 2 place_constraints... promote_globals... promoted vga_clk, 210 / 210 promoted $abc$6850$auto$dff2dffe.cc:175:make_patterns_logic$5273, 64 / 64 promoted reset, 20 / 20 promoted $abc$6850$auto$dff2dffe.cc:158:make_patterns_logic$5267, 19 / 19 promoted $abc$6850$auto$dff2dffe.cc:158:make_patterns_logic$5258, 16 / 16 promoted ps2_clk_pos, 13 / 13 promoted $abc$6850$auto$rtlil.cc:1836:Or$803, 12 / 12 promoted $abc$6850$auto$dff2dffe.cc:158:make_patterns_logic$4774, 10 / 10 promoted 8 nets 3 sr/we 4 cen/wclke 1 clk 8 globals 3 sr/we 4 cen/wclke 1 clk realize_constants... realized 1 place... initial wire length = 16900 at iteration #50: temp = 14.4252, wire length = 11623 at iteration #100: temp = 9.09149, wire length = 8230 at iteration #150: temp = 4.66705, wire length = 5766 at iteration #200: temp = 2.39579, wire length = 3525 at iteration #250: temp = 1.00173, wire length = 2266 at iteration #300: temp = 0.00990195, wire length = 1594 final wire length = 1567 After placement: PIOs 15 / 206 PLBs 180 / 960 BRAMs 0 / 32 place time 6.59s route... pass 1, 0 shared. After routing: span_4 733 / 29696 span_12 144 / 5632 route time 2.76s write_txt example.asc... icetime -d hx8k -mtr example.rpt example.asc icepack example.asc example.bin // Reading input .asc file.. // Reading 8k chipdb file.. // Creating timing netlist.. // Timing estimate: 18.52 ns (54.00 MHz) rm example.blif example.asc gmake[1]: Leaving directory '/construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video' -------------------------------------------------------------------------------- -- Phase: run-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: stage -------------------------------------------------------------------------------- ===> Staging for lattice-ice40-examples-hx8k-g20180310 ===> Generating temporary packing list install -m 0644 /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb/example.v /construction/devel/lattice-ice40-examples-hx8k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx8k-blinky.v install -m 0644 /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb/example.rpt /construction/devel/lattice-ice40-examples-hx8k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx8k-blinky.rpt install -m 0644 /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb/example.bin /construction/devel/lattice-ice40-examples-hx8k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx8k-blinky.bin install -m 0644 /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video/example.v /construction/devel/lattice-ice40-examples-hx8k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx8k-vga-ps2.v install -m 0644 /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video/example.rpt /construction/devel/lattice-ice40-examples-hx8k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx8k-vga-ps2.rpt install -m 0644 /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video/example.bin /construction/devel/lattice-ice40-examples-hx8k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx8k-vga-ps2.bin ====> Compressing man pages (compress-man) -------------------------------------------------------------------------------- -- Phase: package -------------------------------------------------------------------------------- ===> Building package for lattice-ice40-examples-hx8k-g20180310 file sizes/checksums [9]: . done packing files [9]: . done packing directories [0]: . done -------------------------------------------------- -- Termination -------------------------------------------------- Finished: Tuesday, 23 JUL 2019 at 06:38:50 UTC Duration: 00:02:08