=> Building devel/lattice-ice40-examples-hx8k Started : Sunday, 7 JUL 2019 at 17:43:54 UTC Platform: 5.7-DEVELOPMENT DragonFly v5.7.0.83.g49866-DEVELOPMENT #40: Sun Jun 30 03:00:04 PDT 2019 root@pkgbox64.dragonflybsd.org:/usr/obj/usr/src/sys/X86_64_GENERIC x86_64 -------------------------------------------------- -- Environment -------------------------------------------------- UNAME_r=5.4-SYNTH UNAME_m=x86_64 UNAME_p=x86_64 UNAME_v=DragonFly 5.4-SYNTH UNAME_s=DragonFly PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin SSL_NO_VERIFY_PEER=1 TERM=dumb PKG_CACHEDIR=/var/cache/pkg8 PKG_DBDIR=/var/db/pkg8 PORTSDIR=/xports LANG=C HOME=/root USER=root -------------------------------------------------- -- Options -------------------------------------------------- -------------------------------------------------- -- CONFIGURE_ENV -------------------------------------------------- MAKE=gmake XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin SHELL=/bin/sh CONFIG_SHELL=/bin/sh CCVER=gcc80 -------------------------------------------------- -- CONFIGURE_ARGS -------------------------------------------------- -------------------------------------------------- -- MAKE_ENV -------------------------------------------------- XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" -------------------------------------------------- -- MAKE_ARGS -------------------------------------------------- DESTDIR=/construction/devel/lattice-ice40-examples-hx8k/stage -------------------------------------------------- -- PLIST_SUB -------------------------------------------------- OSREL=5.4 PREFIX=%D LOCALBASE=/usr/local RESETPREFIX=/usr/local LIB32DIR=lib PROFILE="@comment " DOCSDIR="share/doc/lattice-ice40-examples-hx8k" EXAMPLESDIR="share/examples/lattice-ice40-olimex" DATADIR="share/lattice-ice40-examples-hx8k" WWWDIR="www/lattice-ice40-examples-hx8k" ETCDIR="etc/lattice-ice40-examples-hx8k" -------------------------------------------------- -- SUB_LIST -------------------------------------------------- PREFIX=/usr/local LOCALBASE=/usr/local DATADIR=/usr/local/share/lattice-ice40-examples-hx8k DOCSDIR=/usr/local/share/doc/lattice-ice40-examples-hx8k EXAMPLESDIR=/usr/local/share/examples/lattice-ice40-olimex WWWDIR=/usr/local/www/lattice-ice40-examples-hx8k ETCDIR=/usr/local/etc/lattice-ice40-examples-hx8k -------------------------------------------------- -- /etc/make.conf -------------------------------------------------- SYNTHPROFILE=Release-5.4 USE_PACKAGE_DEPENDS_ONLY=yes PACKAGE_BUILDING=yes BATCH=yes PKG_CREATE_VERBOSE=yes PORTSDIR=/xports DISTDIR=/distfiles WRKDIRPREFIX=/construction PORT_DBDIR=/options PACKAGES=/packages MAKE_JOBS_NUMBER_LIMIT=5 HAVE_COMPAT_IA32_KERN= CONFIGURE_MAX_CMD_LEN=262144 _PERL5_FROM_BIN=5.28.1 _ALTCCVERSION_921dbbb2=none _OBJC_ALTCCVERSION_921dbbb2=none _SMP_CPUS=8 UID=0 ARCH=x86_64 OPSYS=DragonFly DFLYVERSION=500400 OSVERSION=9999999 OSREL=5.4 _OSRELEASE=5.4-SYNTH PYTHONBASE=/usr/local _PKG_CHECKED=1 -------------------------------------------------------------------------------- -- Phase: check-sanity -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user -------------------------------------------------------------------------------- -- Phase: pkg-depends -------------------------------------------------------------------------------- ===> lattice-ice40-examples-hx8k-g20180310 depends on file: /usr/local/sbin/pkg - not found ===> Installing existing package /packages/All/pkg-1.11.1.txz Installing pkg-1.11.1... Extracting pkg-1.11.1: .......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on file: /usr/local/sbin/pkg - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: fetch-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: fetch -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310 for building -------------------------------------------------------------------------------- -- Phase: checksum -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310 for building => SHA256 Checksum OK for OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz. -------------------------------------------------------------------------------- -- Phase: extract-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: extract -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx8k-g20180310 for building ===> Extracting for lattice-ice40-examples-hx8k-g20180310 => SHA256 Checksum OK for OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz. -------------------------------------------------------------------------------- -- Phase: patch-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: patch -------------------------------------------------------------------------------- ===> Patching for lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: build-depends -------------------------------------------------------------------------------- ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: abc - not found ===> Installing existing package /packages/All/abc-g20180420_1.txz Installing abc-g20180420_1... `-- Installing readline-8.0.0... | `-- Installing indexinfo-0.3.1... | `-- Extracting indexinfo-0.3.1: .... done | `-- Installing ncurses-6.1.20190525... | `-- Extracting ncurses-6.1.20190525: .......... done `-- Extracting readline-8.0.0: .......... done Extracting abc-g20180420_1: ....... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: abc - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: arachne-pnr - not found ===> Installing existing package /packages/All/arachne-pnr-g20181021_1.txz Installing arachne-pnr-g20181021_1... Extracting arachne-pnr-g20181021_1: ......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: arachne-pnr - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: icepack - not found ===> Installing existing package /packages/All/icestorm-g20181021_1.txz Installing icestorm-g20181021_1... `-- Installing libftdi1-1.4_11... | `-- Installing boost-libs-1.70.0_2... | | `-- Installing icu-64.2,1... | | `-- Extracting icu-64.2,1: .......... done | `-- Extracting boost-libs-1.70.0_2: .......... done | `-- Installing gettext-runtime-0.20.1... | `-- Extracting gettext-runtime-0.20.1: .......... done | `-- Installing libconfuse-3.2.1_1... | `-- Extracting libconfuse-3.2.1_1: .......... done | `-- Installing python27-2.7.16_1... | | `-- Installing expat-2.2.6_1... | | `-- Extracting expat-2.2.6_1: .......... done | | `-- Installing libffi-3.2.1_3... | | `-- Extracting libffi-3.2.1_3: .......... done | | `-- Installing libressl-2.9.2... | | `-- Extracting libressl-2.9.2: .......... done | `-- Extracting python27-2.7.16_1: .......... done `-- Extracting libftdi1-1.4_11: .......... done `-- Installing python36-3.6.8_2... `-- Extracting python36-3.6.8_2: .......... done Extracting icestorm-g20181021_1: .......... done Message from boost-libs-1.70.0_2: You have built the Boost library with thread support. Don't forget to add -pthread to your linker options when linking your code. Message from python27-2.7.16_1: =========================================================================== Note that some standard Python modules are provided as separate ports as they require additional dependencies. They are available as: bsddb databases/py-bsddb gdbm databases/py-gdbm sqlite3 databases/py-sqlite3 tkinter x11-toolkits/py-tkinter =========================================================================== Message from python36-3.6.8_2: =========================================================================== Note that some standard Python modules are provided as separate ports as they require additional dependencies. They are available as: py36-gdbm databases/py-gdbm@py36 py36-sqlite3 databases/py-sqlite3@py36 py36-tkinter x11-toolkits/py-tkinter@py36 =========================================================================== ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: icepack - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: yosys - not found ===> Installing existing package /packages/All/yosys-0.8_2.txz Installing yosys-0.8_2... `-- Installing tcl86-8.6.9_1... `-- Extracting tcl86-8.6.9_1: .......... done Extracting yosys-0.8_2: .......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: yosys - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: gmake - not found ===> Installing existing package /packages/All/gmake-4.2.1_3.txz Installing gmake-4.2.1_3... Extracting gmake-4.2.1_3: .......... done ===> lattice-ice40-examples-hx8k-g20180310 depends on executable: gmake - found ===> Returning to build of lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: lib-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: configure -------------------------------------------------------------------------------- ===> Configuring for lattice-ice40-examples-hx8k-g20180310 -------------------------------------------------------------------------------- -- Phase: build -------------------------------------------------------------------------------- ===> Building for lattice-ice40-examples-hx8k-g20180310 /usr/bin/env XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -j5 -C /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb gmake[1]: Entering directory '/construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb' yosys -p 'synth_ice40 -top top -blif example.blif' example.v /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 UNKNOWN, c++ 8.1 -O2 -fno-strict-aliasing -fPIC -Os) -- Parsing `example.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `example.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. -- Running command `synth_ice40 -top top -blif example.blif' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Analyzing design hierarchy.. Top module: \top 2.2.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$example.v:23$20'. Set init value: \mode = 1'1 Found init rule in `\top.$proc$example.v:22$19'. Set init value: \rst_cnt = 15'000000000000000 2.3.4. Executing PROC_ARST pass (detect async resets in processes). 2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$proc$example.v:23$20'. 1/1: $1\mode[0:0] Creating decoders for process `\top.$proc$example.v:22$19'. 1/1: $1\rst_cnt[14:0] Creating decoders for process `\top.$proc$example.v:38$5'. 1/9: $0\LED2_m0_r[0:0] 2/9: $0\LED1_m0_r[0:0] 3/9: $0\cntr[14:0] 4/9: $0\BUT2_r[0:0] 5/9: $0\BUT1_r[0:0] 6/9: $0\mode[0:0] 7/9: $0\rst_cnt[14:0] 8/9: $0\LED2_m1_r[0:0] 9/9: $0\LED1_m1_r[0:0] Creating decoders for process `\top.$proc$example.v:34$3'. 1/1: $0\clk_div[11:0] 2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\BUT1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$45' with positive edge clock. Creating register for signal `\top.\BUT2_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$46' with positive edge clock. Creating register for signal `\top.\LED1_m0_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$47' with positive edge clock. Creating register for signal `\top.\LED2_m0_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$48' with positive edge clock. Creating register for signal `\top.\LED1_m1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$49' with positive edge clock. Creating register for signal `\top.\LED2_m1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$50' with positive edge clock. Creating register for signal `\top.\cntr' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$51' with positive edge clock. Creating register for signal `\top.\rst_cnt' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$52' with positive edge clock. Creating register for signal `\top.\mode' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$53' with positive edge clock. Creating register for signal `\top.\clk_div' using process `\top.$proc$example.v:34$3'. created $dff cell `$procdff$54' with positive edge clock. 2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$proc$example.v:23$20'. Removing empty process `top.$proc$example.v:22$19'. Found and cleaned up 4 empty switches in `\top.$proc$example.v:38$5'. Removing empty process `top.$proc$example.v:38$5'. Removing empty process `top.$proc$example.v:34$3'. Cleaned up 4 empty switches. 2.4. Executing FLATTEN pass (flatten design). No more expansions possible. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing SYNTH pass. 2.7.1. Executing PROC pass (convert processes to netlists). 2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.7.1.3. Executing PROC_INIT pass (extract init attributes). 2.7.1.4. Executing PROC_ARST pass (detect async resets in processes). 2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs). 2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.7.2. Executing OPT_EXPR pass (perform const folding). Replacing $eq cell `$eq$example.v:43$7' in module `top' with inverter. Replacing $eq cell `$eq$example.v:47$9' in module `top' with inverter. Replacing $eq cell `$eq$example.v:47$10' in module `top' with inverter. Replacing $eq cell `$eq$example.v:47$12' (1) in module `\top' with constant driver `$eq$example.v:47$12_Y = \reset'. Optimizing away select inverter for $mux cell `$procmux$28' in module `top'. 2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$not' cell `$eq$example.v:43$7'. removed 24 unused temporary wires. Removed 1 unused cells and 24 unused wires. 2.7.4. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.7.5. Executing OPT pass (performing simple optimizations). 2.7.5.1. Executing OPT_EXPR pass (perform const folding). 2.7.5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$not$example.v:52$15' is identical to cell `$eq$example.v:47$9'. Redirecting output \Y: $0\LED1_m0_r[0:0] = $eq$example.v:47$9_Y Removing $not cell `$not$example.v:52$15' from module `\top'. Cell `$not$example.v:53$16' is identical to cell `$eq$example.v:47$10'. Redirecting output \Y: $0\LED2_m0_r[0:0] = $eq$example.v:47$10_Y Removing $not cell `$not$example.v:53$16' from module `\top'. Removed a total of 2 cells. 2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Replacing known input bits on port B of cell $procmux$28: \rst_cnt -> { 1'1 \rst_cnt [13:0] } Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.7.5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removed 2 unused temporary wires. Removed 1 unused cells and 26 unused wires. 2.7.5.8. Executing OPT_EXPR pass (perform const folding). 2.7.5.9. Finished OPT passes. (There is nothing left to do.) 2.7.6. Executing WREDUCE pass (reducing word size of cells). Removed top 11 bits (of 12) from port B of cell top.$add$example.v:35$4 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:41$6 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:44$8 ($add). Removed top 1 bits (of 15) from port B of cell top.$eq$example.v:55$17 ($eq). 2.7.7. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $add$example.v:35$4 ($add). creating $macc model for $add$example.v:41$6 ($add). creating $macc model for $add$example.v:44$8 ($add). creating $alu model for $macc $add$example.v:44$8. creating $alu model for $macc $add$example.v:41$6. creating $alu model for $macc $add$example.v:35$4. creating $alu model for $gt$example.v:59$18 ($gt): new $alu creating $alu cell for $gt$example.v:59$18: $auto$alumacc.cc:474:replace_alu$56 creating $alu cell for $add$example.v:35$4: $auto$alumacc.cc:474:replace_alu$67 creating $alu cell for $add$example.v:41$6: $auto$alumacc.cc:474:replace_alu$70 creating $alu cell for $add$example.v:44$8: $auto$alumacc.cc:474:replace_alu$73 created 4 $alu and 0 $macc cells. 2.7.8. Executing SHARE pass (SAT-based resource sharing). 2.7.9. Executing OPT pass (performing simple optimizations). 2.7.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing away select inverter for $mux cell `$procmux$22' in module `top'. Optimizing away select inverter for $mux cell `$procmux$37' in module `top'. Optimizing away select inverter for $mux cell `$procmux$43' in module `top'. 2.7.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$59: { $auto$alumacc.cc:490:replace_alu$57 [0] $auto$alumacc.cc:490:replace_alu$57 [1] $auto$alumacc.cc:490:replace_alu$57 [2] $auto$alumacc.cc:490:replace_alu$57 [3] $auto$alumacc.cc:490:replace_alu$57 [4] $auto$alumacc.cc:490:replace_alu$57 [5] $auto$alumacc.cc:490:replace_alu$57 [6] $auto$alumacc.cc:490:replace_alu$57 [7] $auto$alumacc.cc:490:replace_alu$57 [8] $auto$alumacc.cc:490:replace_alu$57 [9] $auto$alumacc.cc:490:replace_alu$57 [10] $auto$alumacc.cc:490:replace_alu$57 [11] $auto$alumacc.cc:490:replace_alu$57 [12] $auto$alumacc.cc:490:replace_alu$57 [13] $auto$alumacc.cc:490:replace_alu$57 [14] } Optimizing cells in module \top. Performed a total of 1 changes. 2.7.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$not' cell `$auto$alumacc.cc:58:get_gt$65'. removed 2 unused temporary wires. Removed 2 unused cells and 28 unused wires. 2.7.9.8. Executing OPT_EXPR pass (perform const folding). 2.7.9.9. Rerunning OPT passes. (Maybe there is more to do..) 2.7.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.7.9.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.9.15. Executing OPT_EXPR pass (perform const folding). 2.7.9.16. Finished OPT passes. (There is nothing left to do.) 2.7.10. Executing FSM pass (extract and optimize FSM). 2.7.10.1. Executing FSM_DETECT pass (finding FSMs in design). 2.7.10.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.7.10.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.7.10.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.10.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.7.10.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.7.10.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.7.10.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.7.11. Executing OPT pass (performing simple optimizations). 2.7.11.1. Executing OPT_EXPR pass (perform const folding). 2.7.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.11.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.11.5. Finished fast OPT passes. 2.7.12. Executing MEMORY pass. 2.7.12.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 2.7.12.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.12.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.12.5. Executing MEMORY_COLLECT pass (generating $mem cells). 2.7.13. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). 2.9. Executing TECHMAP pass (map to technology primitives). 2.9.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. No more expansions possible. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.10.5. Finished fast OPT passes. 2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). 2.12.9. Finished OPT passes. (There is nothing left to do.) 2.13. Executing TECHMAP pass (map to technology primitives). 2.13.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.13.2. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. Mapping top.$ternary$example.v:30$1 ($mux) with simplemap. Mapping top.$ternary$example.v:31$2 ($mux) with simplemap. 2.13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 15 Parameter \B_WIDTH = 15 Parameter \Y_WIDTH = 15 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=15\B_WIDTH=15\Y_WIDTH=15'. 2.13.4. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$56 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=15\B_WIDTH=15\Y_WIDTH=15. Mapping top.$eq$example.v:47$9 ($not) with simplemap. Mapping top.$eq$example.v:47$10 ($not) with simplemap. Mapping top.$logic_and$example.v:47$11 ($logic_and) with simplemap. Mapping top.$logic_and$example.v:47$13 ($logic_and) with simplemap. Mapping top.$xor$example.v:48$14 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$59 ($reduce_and) with simplemap. Mapping top.$eq$example.v:55$17 ($eq) with simplemap. 2.13.5. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 15 Parameter \Y_WIDTH = 15 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=15\Y_WIDTH=15'. 2.13.6. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$73 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=15\Y_WIDTH=15. Mapping top.$procmux$22 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$70 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=15\Y_WIDTH=15. Mapping top.$procmux$25 ($mux) with simplemap. Mapping top.$procmux$28 ($mux) with simplemap. 2.13.7. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 12 Parameter \Y_WIDTH = 12 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=12\Y_WIDTH=12'. 2.13.8. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$67 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=12\Y_WIDTH=12. Mapping top.$procmux$31 ($mux) with simplemap. Mapping top.$procmux$34 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$63 ($or) with simplemap. Mapping top.$procmux$37 ($mux) with simplemap. Mapping top.$procmux$40 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$61 ($not) with simplemap. Mapping top.$procmux$43 ($mux) with simplemap. Mapping top.$procdff$45 ($dff) with simplemap. Mapping top.$procdff$46 ($dff) with simplemap. Mapping top.$procdff$47 ($dff) with simplemap. Mapping top.$procdff$48 ($dff) with simplemap. Mapping top.$procdff$49 ($dff) with simplemap. Mapping top.$procdff$50 ($dff) with simplemap. Mapping top.$procdff$51 ($dff) with simplemap. Mapping top.$procdff$52 ($dff) with simplemap. Mapping top.$procdff$53 ($dff) with simplemap. Mapping top.$procdff$54 ($dff) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$56.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$56.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$73.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$193 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$73.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$73.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$70.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$193 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$70.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$70.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$67.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$227 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$67.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$67.A_conv ($pos) with simplemap. No more expansions possible. 2.14. Executing ICE40_OPT pass (performing simple optimizations). 2.14.1. Running ICE40 specific optimizations. 2.14.2. Executing OPT_EXPR pass (perform const folding). Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$330' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$315' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [0] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$343' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [13] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$328' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [13] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$344' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [14] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$329' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [14] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$314' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [14] = \cntr [14]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$341' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [11] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$326' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [11] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$311' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [11] = \cntr [11]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$342' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [12] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$327' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [12] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$312' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [12] = \cntr [12]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$339' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [9] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$324' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [9] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$309' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [9] = \cntr [9]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$340' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [10] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$325' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [10] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$310' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [10] = \cntr [10]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$337' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$322' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$338' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [8] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$323' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [8] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$308' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [8] = \cntr [8]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$335' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$320' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$336' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$321' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [6] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$306' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [6] = \cntr [6]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$333' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$318' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [3] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$303' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [3] = \cntr [3]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$334' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [4] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$319' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [4] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$304' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [4] = \cntr [4]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$331' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [1] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$316' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [1] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$301' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [1] = \cntr [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$332' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [2] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$317' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [2] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$302' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [2] = \cntr [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$160' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [4] = \cntr [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$162' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [6] = \cntr [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$168' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [12] = \cntr [12]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$170' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [14] = \cntr [14]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$245' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$248' in module `top'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$360' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [0] = \rst_cnt [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$361' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [1] = \rst_cnt [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$346' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [1] = \rst_cnt [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$362' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [2] = \rst_cnt [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$347' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [2] = \rst_cnt [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$363' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [3] = \rst_cnt [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$348' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [3] = \rst_cnt [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$364' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [4] = \rst_cnt [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$349' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [4] = \rst_cnt [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$365' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [5] = \rst_cnt [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$350' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [5] = \rst_cnt [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$366' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [6] = \rst_cnt [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$351' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [6] = \rst_cnt [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$367' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [7] = \rst_cnt [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$352' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [7] = \rst_cnt [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$368' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [8] = \rst_cnt [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$353' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [8] = \rst_cnt [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$369' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [9] = \rst_cnt [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$354' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [9] = \rst_cnt [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$370' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [10] = \rst_cnt [10]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$355' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [10] = \rst_cnt [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$371' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [11] = \rst_cnt [11]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$356' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [11] = \rst_cnt [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$372' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [12] = \rst_cnt [12]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$357' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [12] = \rst_cnt [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$373' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [13] = \rst_cnt [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$358' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [13] = \rst_cnt [13]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$374' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [14] = \rst_cnt [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$359' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [14] = \rst_cnt [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$405' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [0] = \cntr [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$406' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [1] = \cntr [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$391' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [1] = \cntr [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$407' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [2] = \cntr [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$392' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [2] = \cntr [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$408' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [3] = \cntr [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$393' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [3] = \cntr [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$409' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [4] = \cntr [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$394' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [4] = \cntr [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$410' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [5] = \cntr [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$395' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [5] = \cntr [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$411' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [6] = \cntr [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$396' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [6] = \cntr [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$412' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [7] = \cntr [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$397' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [7] = \cntr [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$413' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [8] = \cntr [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$398' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [8] = \cntr [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$414' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [9] = \cntr [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$399' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [9] = \cntr [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$415' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [10] = \cntr [10]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$400' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [10] = \cntr [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$416' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [11] = \cntr [11]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$401' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [11] = \cntr [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$417' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [12] = \cntr [12]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$402' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [12] = \cntr [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$418' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [13] = \cntr [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$403' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [13] = \cntr [13]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$419' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [14] = \cntr [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$404' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [14] = \cntr [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$447' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [0] = \clk_div [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$448' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [1] = \clk_div [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$436' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [1] = \clk_div [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$449' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [2] = \clk_div [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$437' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [2] = \clk_div [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$450' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [3] = \clk_div [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$438' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [3] = \clk_div [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$451' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [4] = \clk_div [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$439' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [4] = \clk_div [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$452' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [5] = \clk_div [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$440' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [5] = \clk_div [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$453' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [6] = \clk_div [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$441' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [6] = \clk_div [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$454' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [7] = \clk_div [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$442' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [7] = \clk_div [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$455' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [8] = \clk_div [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$443' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [8] = \clk_div [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$456' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [9] = \clk_div [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$444' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [9] = \clk_div [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$457' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [10] = \clk_div [10]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$445' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [10] = \clk_div [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$458' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [11] = \clk_div [11]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$446' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [11] = \clk_div [11]'. 2.14.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$300' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$390'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$300' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$169' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$313'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [13] = $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [13] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$169' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$163' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$307'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [7] = $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [7] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$163' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$161' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$305'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [5] = $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$161' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$156' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$390'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [0] = $techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$156' from module `\top'. Removed a total of 5 cells. 2.14.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[14].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[13].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[12].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[11].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[10].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[0].adder'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$192'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$73.slice[14].carry'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$70.slice[14].carry'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$67.slice[11].carry'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$345'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$375'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$376'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$377'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$378'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$379'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$380'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$381'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$382'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$383'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$384'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$385'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$386'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$387'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$388'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$389'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$420'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$421'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$422'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$423'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$424'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$425'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$426'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$427'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$428'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$429'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$430'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$431'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$432'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$433'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$434'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$435'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$459'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$460'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$461'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$462'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$463'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$464'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$465'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$466'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$467'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$468'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$469'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$470'. removed 70 unused temporary wires. Removed 65 unused cells and 98 unused wires. 2.14.6. Rerunning OPT passes. (Removed registers in this run.) 2.14.7. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$56.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$67.slice[0].carry: CO=\clk_div [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$70.slice[0].carry: CO=\cntr [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$73.slice[0].carry: CO=\rst_cnt [0] Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$67.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$70.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$73.slice[1].adder back to logic. 2.14.8. Executing OPT_EXPR pass (perform const folding). Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$517' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$516' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$522' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$514' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$515' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$521' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$513' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$512' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$520' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$511' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$510' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$519' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$524' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$523 [0] = \rst_cnt [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$498' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$497' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$503' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$496' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$495' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$502' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$494' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$493' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$501' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$492' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$491' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$500' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$505' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$504 [0] = \cntr [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$479' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$478' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$484' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$477' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$476' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$483' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$475' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$474' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$482' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$473' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$472' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$481' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$486' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$485 [0] = \clk_div [1]'. 2.14.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removed 9 unused temporary wires. Removed 65 unused cells and 107 unused wires. 2.14.12. Rerunning OPT passes. (Removed registers in this run.) 2.14.13. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$56.slice[1].carry: CO=\cntr [1] 2.14.14. Executing OPT_EXPR pass (perform const folding). 2.14.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.16. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 65 unused cells and 107 unused wires. 2.14.18. Rerunning OPT passes. (Removed registers in this run.) 2.14.19. Running ICE40 specific optimizations. 2.14.20. Executing OPT_EXPR pass (perform const folding). 2.14.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.22. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 65 unused cells and 107 unused wires. 2.14.24. Finished OPT passes. (There is nothing left to do.) 2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). 2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). Selected cell types for direct conversion: $_DFF_PP1_ -> $__DFFE_PP1 $_DFF_PP0_ -> $__DFFE_PP0 $_DFF_PN1_ -> $__DFFE_PN1 $_DFF_PN0_ -> $__DFFE_PN0 $_DFF_NP1_ -> $__DFFE_NP1 $_DFF_NP0_ -> $__DFFE_NP0 $_DFF_NN1_ -> $__DFFE_NN1 $_DFF_NN0_ -> $__DFFE_NN0 $_DFF_N_ -> $_DFFE_NP_ $_DFF_P_ -> $_DFFE_PP_ Transforming FF to FF+Enable cells in module top: converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$255 to $_DFFE_PP_ for $0\LED1_m1_r[0:0] -> \LED1_m1_r. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$256 to $_DFFE_PP_ for $0\LED2_m1_r[0:0] -> \LED2_m1_r. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$258 to $_DFFE_PP_ for $0\cntr[14:0] [1] -> \cntr [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$272 to $_DFFE_PP_ for $0\rst_cnt[14:0] [0] -> \rst_cnt [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$273 to $_DFFE_PP_ for $0\rst_cnt[14:0] [1] -> \rst_cnt [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$274 to $_DFFE_PP_ for $0\rst_cnt[14:0] [2] -> \rst_cnt [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$275 to $_DFFE_PP_ for $0\rst_cnt[14:0] [3] -> \rst_cnt [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$276 to $_DFFE_PP_ for $0\rst_cnt[14:0] [4] -> \rst_cnt [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$277 to $_DFFE_PP_ for $0\rst_cnt[14:0] [5] -> \rst_cnt [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$278 to $_DFFE_PP_ for $0\rst_cnt[14:0] [6] -> \rst_cnt [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$279 to $_DFFE_PP_ for $0\rst_cnt[14:0] [7] -> \rst_cnt [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$280 to $_DFFE_PP_ for $0\rst_cnt[14:0] [8] -> \rst_cnt [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$281 to $_DFFE_PP_ for $0\rst_cnt[14:0] [9] -> \rst_cnt [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$282 to $_DFFE_PP_ for $0\rst_cnt[14:0] [10] -> \rst_cnt [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$283 to $_DFFE_PP_ for $0\rst_cnt[14:0] [11] -> \rst_cnt [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$284 to $_DFFE_PP_ for $0\rst_cnt[14:0] [12] -> \rst_cnt [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$285 to $_DFFE_PP_ for $0\rst_cnt[14:0] [13] -> \rst_cnt [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$287 to $_DFFE_PP_ for $0\mode[0:0] -> \mode. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$289 to $_DFFE_PP_ for $0\clk_div[11:0] [1] -> \clk_div [1]. 2.17. Executing TECHMAP pass (map to technology primitives). 2.17.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Successfully finished Verilog frontend. Mapping top.$auto$simplemap.cc:420:simplemap_dff$299 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$251 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$252 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$253 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$254 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$255 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$256 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$257 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$258 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$259 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$260 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$261 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$262 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$263 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$264 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$265 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$266 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$267 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$268 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$269 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$270 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$271 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$272 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$273 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$274 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$275 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$276 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$277 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$278 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$279 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$280 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$281 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$282 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$283 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$284 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$285 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$286 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$287 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$288 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$289 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$290 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$291 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$292 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$293 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$294 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$295 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$296 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$297 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$298 using \$_DFF_P_. No more expansions possible. 2.18. Executing OPT_EXPR pass (perform const folding). Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$612' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$609 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$603' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$600 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$594' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$591 [1] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$527' (x??) in module `\top' with constant driver `$add$example.v:44$8_Y [1] = $auto$simplemap.cc:309:simplemap_lut$523 [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$569' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$566 [1] = \rst_cnt [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$568' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$566 [0] = \rst_cnt [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$707' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$705 = \clk_div [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$701' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$699 = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$693' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$690 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$684' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$681 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$581' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$578 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$570' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$566 [2] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$508' (x??) in module `\top' with constant driver `$add$example.v:41$6_Y [1] = $auto$simplemap.cc:309:simplemap_lut$504 [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$550' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$548 [0] = \cntr [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$560' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$557 [1] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$211' (x??) in module `\top' with constant driver `$0\mode[0:0] = $xor$example.v:48$14_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$212' (?x?) in module `\top' with constant driver `$procmux$28_Y [0] = $add$example.v:44$8_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$213' (?x?) in module `\top' with constant driver `$procmux$28_Y [1] = $auto$simplemap.cc:309:simplemap_lut$523 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$214' (?x?) in module `\top' with constant driver `$procmux$28_Y [2] = $add$example.v:44$8_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$489' (x??) in module `\top' with constant driver `$0\clk_div[11:0] [1] = $auto$simplemap.cc:309:simplemap_lut$485 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$215' (?x?) in module `\top' with constant driver `$procmux$28_Y [3] = $add$example.v:44$8_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$216' (?x?) in module `\top' with constant driver `$procmux$28_Y [4] = $add$example.v:44$8_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$217' (?x?) in module `\top' with constant driver `$procmux$28_Y [5] = $add$example.v:44$8_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$218' (?x?) in module `\top' with constant driver `$procmux$28_Y [6] = $add$example.v:44$8_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$219' (?x?) in module `\top' with constant driver `$procmux$28_Y [7] = $add$example.v:44$8_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$220' (?x?) in module `\top' with constant driver `$procmux$28_Y [8] = $add$example.v:44$8_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$221' (?x?) in module `\top' with constant driver `$procmux$28_Y [9] = $add$example.v:44$8_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$222' (?x?) in module `\top' with constant driver `$procmux$28_Y [10] = $add$example.v:44$8_Y [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$223' (?x?) in module `\top' with constant driver `$procmux$28_Y [11] = $add$example.v:44$8_Y [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$224' (?x?) in module `\top' with constant driver `$procmux$28_Y [12] = $add$example.v:44$8_Y [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$225' (?x?) in module `\top' with constant driver `$procmux$28_Y [13] = $add$example.v:44$8_Y [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$675' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$672 [1] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$245' (1x?) in module `\top' with constant driver `$procmux$34_Y = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$247' (01?) in module `\top' with constant driver `$0\LED2_m1_r[0:0] = $auto$rtlil.cc:1698:Or$64'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$248' (0x?) in module `\top' with constant driver `$procmux$40_Y = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$666' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$663 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$657' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$654 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$648' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$645 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$639' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$636 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$630' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$627 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$621' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$618 [1] = $logic_and$example.v:47$13_Y'. 2.19. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.20. Executing ICE40_FFINIT pass (implement FF init values). Handling FF init values in top. FF init value for cell $auto$simplemap.cc:420:simplemap_dff$272 (SB_DFFE): \rst_cnt [0] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$273 (SB_DFFE): \rst_cnt [1] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$274 (SB_DFFE): \rst_cnt [2] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$275 (SB_DFFE): \rst_cnt [3] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$276 (SB_DFFE): \rst_cnt [4] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$277 (SB_DFFE): \rst_cnt [5] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$278 (SB_DFFE): \rst_cnt [6] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$279 (SB_DFFE): \rst_cnt [7] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$280 (SB_DFFE): \rst_cnt [8] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$281 (SB_DFFE): \rst_cnt [9] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$282 (SB_DFFE): \rst_cnt [10] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$283 (SB_DFFE): \rst_cnt [11] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$284 (SB_DFFE): \rst_cnt [12] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$285 (SB_DFFE): \rst_cnt [13] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$286 (SB_DFF): \rst_cnt [14] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$287 (SB_DFFE): \mode = 1 2.21. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells). Merging set/reset $_MUX_ cells into SB_FFs in top. Merging $auto$simplemap.cc:277:simplemap_mux$196 (A=1'0, B=$add$example.v:41$6_Y [0], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$257 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$197 (A=1'0, B=$auto$simplemap.cc:309:simplemap_lut$504 [1], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$258 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$198 (A=1'0, B=$add$example.v:41$6_Y [2], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$259 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$199 (A=1'0, B=$add$example.v:41$6_Y [3], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$260 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$200 (A=1'0, B=$add$example.v:41$6_Y [4], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$261 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$201 (A=1'0, B=$add$example.v:41$6_Y [5], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$262 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$202 (A=1'0, B=$add$example.v:41$6_Y [6], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$263 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$203 (A=1'0, B=$add$example.v:41$6_Y [7], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$264 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$204 (A=1'0, B=$add$example.v:41$6_Y [8], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$265 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$205 (A=1'0, B=$add$example.v:41$6_Y [9], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$266 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$206 (A=1'0, B=$add$example.v:41$6_Y [10], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$267 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$207 (A=1'0, B=$add$example.v:41$6_Y [11], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$268 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$208 (A=1'0, B=$add$example.v:41$6_Y [12], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$269 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$209 (A=1'0, B=$add$example.v:41$6_Y [13], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$270 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$210 (A=1'0, B=$add$example.v:41$6_Y [14], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$271 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$230 (A=$add$example.v:44$8_Y [0], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$272 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$231 (A=$auto$simplemap.cc:309:simplemap_lut$523 [1], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$273 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$232 (A=$add$example.v:44$8_Y [2], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$274 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$233 (A=$add$example.v:44$8_Y [3], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$275 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$234 (A=$add$example.v:44$8_Y [4], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$276 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$235 (A=$add$example.v:44$8_Y [5], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$277 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$236 (A=$add$example.v:44$8_Y [6], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$278 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$237 (A=$add$example.v:44$8_Y [7], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$279 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$238 (A=$add$example.v:44$8_Y [8], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$280 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$239 (A=$add$example.v:44$8_Y [9], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$281 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$240 (A=$add$example.v:44$8_Y [10], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$282 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$241 (A=$add$example.v:44$8_Y [11], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$283 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$242 (A=$add$example.v:44$8_Y [12], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$284 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$243 (A=$add$example.v:44$8_Y [13], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$285 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$244 (A=$procmux$28_Y [14], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$286 (SB_DFF). 2.22. Executing ICE40_OPT pass (performing simple optimizations). 2.22.1. Running ICE40 specific optimizations. 2.22.2. Executing OPT_EXPR pass (perform const folding). Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$126' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$127' in module `top'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$196' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$197' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$198' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$199' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$200' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$201' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$202' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$203' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$204' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$205' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$206' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$207' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$208' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$209' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$210' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$226' in module `top' with or-gate. 2.22.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$798' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$799 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$798' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$796' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$797 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$796' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$794' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$795 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$794' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$792' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$793 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$792' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$790' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$791 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$790' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$788' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$789 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$788' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$786' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$787 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$786' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$784' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$785 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$784' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$782' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$783 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$782' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$780' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$781 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$780' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$778' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$779 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$778' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$776' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$777 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$776' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$774' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$775 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$774' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$772' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$773 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$772' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$665' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$663 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$665' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$559' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$557 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$559' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$656' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$654 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$656' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$669' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$661 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$669' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$541' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$551'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$539 [0] = $auto$simplemap.cc:250:simplemap_eqne$548 [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$541' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$532' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$551'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$530 [0] = $auto$simplemap.cc:250:simplemap_eqne$548 [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$532' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$533' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$542'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$530 [1] = $auto$simplemap.cc:250:simplemap_eqne$539 [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$533' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$536' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$545'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$528 = $auto$dff2dffe.cc:158:make_patterns_logic$537 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$536' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$692' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$690 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$692' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$660' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$652 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$660' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$647' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$645 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$647' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$638' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$636 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$638' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$642' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$634 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$642' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$629' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$627 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$629' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$580' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$578 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$580' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$633' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$625 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$633' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$620' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$618 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$620' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$624' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$616 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$624' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$611' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$609 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$611' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$602' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$600 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$602' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$687' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$679 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$687' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$606' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$598 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$606' from module `\top'. Cell `$auto$simplemap.cc:277:simplemap_mux$250' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $0\LED1_m1_r[0:0] = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$simplemap.cc:277:simplemap_mux$250' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$651' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$643 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$651' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$593' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$591 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$593' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$674' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$672 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$674' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$615' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$607 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$615' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$563' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$555 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$563' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$584' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$576 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$584' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$678' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$670 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$678' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$696' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$688 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$696' from module `\top'. Removed a total of 45 cells. 2.22.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$196'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$197'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$198'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$199'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$200'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$201'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$202'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$203'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$204'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$205'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$206'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$207'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$208'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$209'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$210'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$230'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$231'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$232'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$233'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$234'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$235'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$236'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$237'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$238'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$239'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$240'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$241'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$242'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$243'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$244'. removed 243 unused temporary wires. Removed 95 unused cells and 350 unused wires. 2.22.6. Rerunning OPT passes. (Removed registers in this run.) 2.22.7. Running ICE40 specific optimizations. 2.22.8. Executing OPT_EXPR pass (perform const folding). 2.22.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.22.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.22.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 95 unused cells and 350 unused wires. 2.22.12. Finished OPT passes. (There is nothing left to do.) 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. No more expansions possible. 2.24. Executing ABC pass (technology mapping using ABC). 2.24.1. Extracting gate netlist of module `\top' to `/input.blif'.. Extracted 64 gates and 93 wires to a netlist network with 28 inputs and 16 outputs. 2.24.1.1. Executing ABC. Running ABC command: abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + write_blif /output.blif 2.24.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 50 ABC RESULTS: internal signals: 49 ABC RESULTS: input signals: 28 ABC RESULTS: output signals: 16 Removing temp directory. Removed 0 unused cells and 59 unused wires. 2.25. Executing TECHMAP pass (map to technology primitives). 2.25.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.25.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'00000001 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'00000001'. 2.25.3. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$811 using $paramod\$lut\WIDTH=3\LUT=8'00000001. 2.25.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 4 Parameter \LUT = 16'1000000000000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'1000000000000000'. 2.25.5. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$810 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$809 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. 2.25.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 4 Parameter \LUT = 16'0100000000000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0100000000000000'. 2.25.7. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$808 using $paramod\$lut\WIDTH=4\LUT=16'0100000000000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$807 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. 2.25.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 2 Parameter \LUT = 4'0100 Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'0100'. 2.25.9. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$806 using $paramod\$lut\WIDTH=2\LUT=4'0100. 2.25.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 4 Parameter \LUT = 16'0001000000000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0001000000000000'. 2.25.11. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$815 using $paramod\$lut\WIDTH=4\LUT=16'0001000000000000. 2.25.12. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'10000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'10000000'. 2.25.13. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$816 using $paramod\$lut\WIDTH=3\LUT=8'10000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$814 using $paramod\$lut\WIDTH=4\LUT=16'0001000000000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$813 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. 2.25.14. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'11110100 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'11110100'. 2.25.15. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$817 using $paramod\$lut\WIDTH=3\LUT=8'11110100. 2.25.16. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'11001010 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'11001010'. 2.25.17. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$821 using $paramod\$lut\WIDTH=3\LUT=8'11001010. 2.25.18. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 2 Parameter \LUT = 4'1011 Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'1011'. 2.25.19. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$825 using $paramod\$lut\WIDTH=2\LUT=4'1011. 2.25.20. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 1 Parameter \LUT = 2'01 Generating RTLIL representation for module `$paramod\$lut\WIDTH=1\LUT=2'01'. 2.25.21. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$826 using $paramod\$lut\WIDTH=1\LUT=2'01. 2.25.22. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'00010000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'00010000'. 2.25.23. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$818 using $paramod\$lut\WIDTH=3\LUT=8'00010000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$819 using $paramod\$lut\WIDTH=2\LUT=4'1011. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$829 using $paramod\$lut\WIDTH=1\LUT=2'01. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$827 using $paramod\$lut\WIDTH=1\LUT=2'01. 2.25.24. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 2 Parameter \LUT = 4'1110 Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'1110'. 2.25.25. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$823 using $paramod\$lut\WIDTH=2\LUT=4'1110. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$812 using $paramod\$lut\WIDTH=3\LUT=8'11110100. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$830 using $paramod\$lut\WIDTH=1\LUT=2'01. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$820 using $paramod\$lut\WIDTH=3\LUT=8'11110100. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$824 using $paramod\$lut\WIDTH=1\LUT=2'01. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$822 using $paramod\$lut\WIDTH=3\LUT=8'11001010. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$828 using $paramod\$lut\WIDTH=1\LUT=2'01. No more expansions possible. Removed 0 unused cells and 50 unused wires. 2.26. Executing HIERARCHY pass (managing design hierarchy). 2.26.1. Analyzing design hierarchy.. Top module: \top 2.26.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.26.3. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'0100 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'0100'. 2.26.4. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.5. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0100000000000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0100000000000000'. 2.26.6. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.7. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.8. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'00000001 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'00000001'. 2.26.9. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11110100 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11110100'. 2.26.10. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.11. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0001000000000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0001000000000000'. 2.26.12. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0001000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0001000000000000'. 2.26.13. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'10000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10000000'. 2.26.14. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11110100 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11110100'. 2.26.15. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'00010000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'00010000'. 2.26.16. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'1011 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'1011'. 2.26.17. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11110100 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11110100'. 2.26.18. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11001010 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11001010'. 2.26.19. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11001010 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11001010'. 2.26.20. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'1110 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'1110'. 2.26.21. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.22. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'1011 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'1011'. 2.26.23. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.24. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.25. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.26. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.27. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.28. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.29. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.30. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.31. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.32. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.33. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.34. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.35. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.36. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.37. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.38. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.39. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.40. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.41. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.42. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.43. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.44. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.45. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.46. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.47. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.48. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.49. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.50. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.51. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.52. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.53. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.54. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.55. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.56. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.57. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.58. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.59. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.60. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.61. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.62. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.63. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.64. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.65. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.66. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.27. Printing statistics. === top === Number of wires: 48 Number of wire bits: 179 Number of public wires: 16 Number of public wire bits: 55 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 162 SB_CARRY 49 SB_DFF 15 SB_DFFE 4 SB_DFFESR 15 SB_DFFSR 15 SB_LUT4 64 2.28. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.29. Executing BLIF backend. End of script. Logfile hash: b2348668fd CPU: user 0.68s system 0.04s, MEM: 55.56 MB total, 47.35 MB resident Yosys 0.8 (git sha1 UNKNOWN, c++ 8.1 -O2 -fno-strict-aliasing -fPIC -Os) Time spent: 42% 9x read_verilog (0 sec), 8% 17x opt_expr (0 sec), ... arachne-pnr -d 8k -o example.asc -p ice40hx8k-evb.pcf example.blif -P ct256 seed: 1 device: 8k read_chipdb +/share/arachne-pnr/chipdb-8k.bin... supported packages: bg121, bg121:4k, cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k read_blif example.blif... prune... read_pcf ice40hx8k-evb.pcf... instantiate_io... pack... After packing: IOs 5 / 206 GBs 0 / 8 GB_IOs 0 / 8 LCs 89 / 7680 DFF 16 CARRY 20 CARRY, DFF 33 DFF PASS 3 CARRY PASS 6 BRAMs 0 / 32 WARMBOOTs 0 / 1 PLLs 0 / 2 place_constraints... promote_globals... promoted clk_24KHz, 38 / 38 promoted $abc$805$n64, 17 / 18 promoted $0\LED1_m1_r[0:0], 16 / 16 promoted $abc$805$n66, 13 / 13 promoted CLK$2, 12 / 12 promoted 5 nets 2 sr/we 1 cen/wclke 2 clk 5 globals 2 sr/we 1 cen/wclke 2 clk realize_constants... realized 1 place... initial wire length = 1556 at iteration #50: temp = 15.1845, wire length = 780 at iteration #100: temp = 8.63692, wire length = 660 at iteration #150: temp = 2.9414, wire length = 340 at iteration #200: temp = 0.843561, wire length = 217 final wire length = 179 After placement: PIOs 8 / 206 PLBs 25 / 960 BRAMs 0 / 32 place time 0.28s route... pass 1, 0 shared. After routing: span_4 35 / 29696 span_12 18 / 5632 route time 0.22s write_txt example.asc... icetime -d hx8k -mtr example.rpt example.asc icepack example.asc example.bin // Reading input .asc file.. // Reading 8k chipdb file.. // Creating timing netlist.. // Timing estimate: 8.39 ns (119.19 MHz) rm example.blif example.asc gmake[1]: Leaving directory '/construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40hx8k-evb' /usr/bin/env XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx8k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx8k HOME=/construction/devel/lattice-ice40-examples-hx8k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx8k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -j5 -C /construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video gmake[1]: Entering directory '/construction/devel/lattice-ice40-examples-hx8k/iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612/demo/ice40-io-video' yosys -p 'synth_ice40 -top top -blif example.blif' example.v /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 UNKNOWN, c++ 8.1 -O2 -fno-strict-aliasing -fPIC -Os) -- Parsing `example.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `example.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. -- Running command `synth_ice40 -top top -blif example.blif' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Analyzing design hierarchy.. Top module: \top 2.2.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$example.v:96$224'. Set init value: \r_arr = 1'0 Found init rule in `\top.$proc$example.v:95$223'. Set init value: \d_arr = 1'0 Found init rule in `\top.$proc$example.v:94$222'. Set init value: \l_arr = 1'0 Found init rule in `\top.$proc$example.v:93$221'. Set init value: \u_arr = 1'0 Found init rule in `\top.$proc$example.v:63$220'. Set init value: \reset = 1'1 Found init rule in `\top.$proc$example.v:62$219'. Set init value: \timer_t = 8'00000000 2.3.4. Executing PROC_ARST pass (detect async resets in processes). 2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$proc$example.v:96$224'. 1/1: $1\r_arr[0:0] Creating decoders for process `\top.$proc$example.v:95$223'. 1/1: $1\d_arr[0:0] Creating decoders for process `\top.$proc$example.v:94$222'. 1/1: $1\l_arr[0:0] Creating decoders for process `\top.$proc$example.v:93$221'. 1/1: $1\u_arr[0:0] Creating decoders for process `\top.$proc$example.v:63$220'. 1/1: $1\reset[0:0] Creating decoders for process `\top.$proc$example.v:62$219'. 1/1: $1\timer_t[7:0] Creating decoders for process `\top.$proc$example.v:110$39'. 1/116: $0\ps2_data_reg[7:0] [7] 2/116: $1$mem2bits$\sq_figure$example.v:308$4[19:0]$176 3/116: $1$mem2bits$\sq_figure$example.v:307$3[19:0]$175 4/116: $1$mem2bits$\sq_figure$example.v:306$2[19:0]$174 5/116: $0\ps2_data_reg[7:0] [4] 6/116: $1$mem2bits$\sq_figure$example.v:309$5[19:0]$177 7/116: $0\ps2_data_reg[7:0] [5] 8/116: $0\ps2_data_reg[7:0] [6] 9/116: $0\ps2_data_reg[7:0] [0] 10/116: $0\ps2_data_reg[7:0] [1] 11/116: $0\ps2_data_reg[7:0] [2] 12/116: $0\ps2_data_reg[7:0] [3] 13/116: $2$mem2bits$\sq_figure$example.v:202$1[19:0]$146 14/116: $1$mem2bits$\sq_figure$example.v:202$1[19:0]$138 15/116: $0$mem2bits$\sq_figure$example.v:309$5[19:0]$44 16/116: $0$mem2bits$\sq_figure$example.v:308$4[19:0]$43 17/116: $0$mem2bits$\sq_figure$example.v:307$3[19:0]$42 18/116: $0$mem2bits$\sq_figure$example.v:306$2[19:0]$41 19/116: $0\arr_timer[20:0] 20/116: $0\ps2_clk_buf[1:0] 21/116: $0$mem2bits$\sq_figure$example.v:202$1[19:0]$40 22/116: $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 23/116: $0$memwr$\sq_figure$example.v:126$6_DATA[19:0]$46 24/116: $0$memwr$\sq_figure$example.v:126$6_ADDR[31:0]$45 25/116: $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 26/116: $0$memwr$\sq_figure$example.v:127$7_DATA[19:0]$49 27/116: $0$memwr$\sq_figure$example.v:127$7_ADDR[31:0]$48 28/116: $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 29/116: $0$memwr$\sq_figure$example.v:128$8_DATA[19:0]$52 30/116: $0$memwr$\sq_figure$example.v:128$8_ADDR[31:0]$51 31/116: $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 32/116: $0$memwr$\sq_figure$example.v:129$9_DATA[19:0]$55 33/116: $0$memwr$\sq_figure$example.v:129$9_ADDR[31:0]$54 34/116: $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 35/116: $0$memwr$\sq_figure$example.v:130$10_DATA[19:0]$58 36/116: $0$memwr$\sq_figure$example.v:130$10_ADDR[31:0]$57 37/116: $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 38/116: $0$memwr$\sq_figure$example.v:131$11_DATA[19:0]$61 39/116: $0$memwr$\sq_figure$example.v:131$11_ADDR[31:0]$60 40/116: $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 41/116: $0$memwr$\sq_figure$example.v:132$12_DATA[19:0]$64 42/116: $0$memwr$\sq_figure$example.v:132$12_ADDR[31:0]$63 43/116: $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 44/116: $0$memwr$\sq_figure$example.v:133$13_DATA[19:0]$67 45/116: $0$memwr$\sq_figure$example.v:133$13_ADDR[31:0]$66 46/116: $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 47/116: $0$memwr$\sq_figure$example.v:134$14_DATA[19:0]$70 48/116: $0$memwr$\sq_figure$example.v:134$14_ADDR[31:0]$69 49/116: $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 50/116: $0$memwr$\sq_figure$example.v:135$15_DATA[19:0]$73 51/116: $0$memwr$\sq_figure$example.v:135$15_ADDR[31:0]$72 52/116: $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 53/116: $0$memwr$\sq_figure$example.v:136$16_DATA[19:0]$76 54/116: $0$memwr$\sq_figure$example.v:136$16_ADDR[31:0]$75 55/116: $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 56/116: $0$memwr$\sq_figure$example.v:137$17_DATA[19:0]$79 57/116: $0$memwr$\sq_figure$example.v:137$17_ADDR[31:0]$78 58/116: $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 59/116: $0$memwr$\sq_figure$example.v:138$18_DATA[19:0]$82 60/116: $0$memwr$\sq_figure$example.v:138$18_ADDR[31:0]$81 61/116: $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 62/116: $0$memwr$\sq_figure$example.v:139$19_DATA[19:0]$85 63/116: $0$memwr$\sq_figure$example.v:139$19_ADDR[31:0]$84 64/116: $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 65/116: $0$memwr$\sq_figure$example.v:140$20_DATA[19:0]$88 66/116: $0$memwr$\sq_figure$example.v:140$20_ADDR[31:0]$87 67/116: $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 68/116: $0$memwr$\sq_figure$example.v:141$21_DATA[19:0]$91 69/116: $0$memwr$\sq_figure$example.v:141$21_ADDR[31:0]$90 70/116: $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 71/116: $0$memwr$\sq_figure$example.v:142$22_DATA[19:0]$94 72/116: $0$memwr$\sq_figure$example.v:142$22_ADDR[31:0]$93 73/116: $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 74/116: $0$memwr$\sq_figure$example.v:143$23_DATA[19:0]$97 75/116: $0$memwr$\sq_figure$example.v:143$23_ADDR[31:0]$96 76/116: $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 77/116: $0$memwr$\sq_figure$example.v:144$24_DATA[19:0]$100 78/116: $0$memwr$\sq_figure$example.v:144$24_ADDR[31:0]$99 79/116: $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 80/116: $0$memwr$\sq_figure$example.v:145$25_DATA[19:0]$103 81/116: $0$memwr$\sq_figure$example.v:145$25_ADDR[31:0]$102 82/116: $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 83/116: $0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 84/116: $0$memwr$\sq_figure$example.v:306$26_ADDR[31:0]$105 85/116: $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 86/116: $0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 87/116: $0$memwr$\sq_figure$example.v:307$27_ADDR[31:0]$108 88/116: $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 89/116: $0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 90/116: $0$memwr$\sq_figure$example.v:308$28_ADDR[31:0]$111 91/116: $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 92/116: $0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 93/116: $0$memwr$\sq_figure$example.v:309$29_ADDR[31:0]$114 94/116: $0\r_arr[0:0] 95/116: $0\d_arr[0:0] 96/116: $0\l_arr[0:0] 97/116: $0\u_arr[0:0] 98/116: $0\ps2_dat_r[10:0] 99/116: $0\ps2_data_reg_prev1[7:0] 100/116: $0\ps2_data_reg_prev[7:0] 101/116: $3$mem2bits$\sq_figure$example.v:202$1[19:0]$154 102/116: $0\ps2_cntr[3:0] 103/116: $0\sq_pos_y[9:0] 104/116: $0\sq_pos_x[9:0] 105/116: $0\disp_en[0:0] 106/116: $0\c_ver[9:0] 107/116: $0\c_hor[9:0] 108/116: $0\c_col[9:0] 109/116: $0\c_row[9:0] 110/116: $0\reset[0:0] 111/116: $0\timer_t[7:0] 112/116: $0\vga_vs_r[0:0] 113/116: $0\vga_hs_r[0:0] 114/116: $0\vga_b_r[2:0] 115/116: $0\vga_g_r[2:0] 116/116: $0\vga_r_r[2:0] Creating decoders for process `\top.$proc$example.v:46$30'. 1/1: $0\clk_div[1:0] 2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\vga_r_r' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$975' with positive edge clock. Creating register for signal `\top.\vga_g_r' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$976' with positive edge clock. Creating register for signal `\top.\vga_b_r' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$977' with positive edge clock. Creating register for signal `\top.\vga_hs_r' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$978' with positive edge clock. Creating register for signal `\top.\vga_vs_r' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$979' with positive edge clock. Creating register for signal `\top.\timer_t' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$980' with positive edge clock. Creating register for signal `\top.\reset' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$981' with positive edge clock. Creating register for signal `\top.\c_row' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$982' with positive edge clock. Creating register for signal `\top.\c_col' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$983' with positive edge clock. Creating register for signal `\top.\c_hor' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$984' with positive edge clock. Creating register for signal `\top.\c_ver' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$985' with positive edge clock. Creating register for signal `\top.\disp_en' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$986' with positive edge clock. Creating register for signal `\top.\sq_pos_x' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$987' with positive edge clock. Creating register for signal `\top.\sq_pos_y' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$988' with positive edge clock. Creating register for signal `\top.\ps2_cntr' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$989' with positive edge clock. Creating register for signal `\top.\ps2_data_reg' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$990' with positive edge clock. Creating register for signal `\top.\ps2_data_reg_prev' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$991' with positive edge clock. Creating register for signal `\top.\ps2_data_reg_prev1' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$992' with positive edge clock. Creating register for signal `\top.\ps2_dat_r' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$993' with positive edge clock. Creating register for signal `\top.\ps2_clk_buf' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$994' with positive edge clock. Creating register for signal `\top.\u_arr' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$995' with positive edge clock. Creating register for signal `\top.\l_arr' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$996' with positive edge clock. Creating register for signal `\top.\d_arr' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$997' with positive edge clock. Creating register for signal `\top.\r_arr' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$998' with positive edge clock. Creating register for signal `\top.\arr_timer' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$999' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:202$1' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1000' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:306$2' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1001' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:307$3' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1002' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:308$4' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1003' with positive edge clock. Creating register for signal `\top.$mem2bits$\sq_figure$example.v:309$5' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1004' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:126$6_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1005' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:126$6_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1006' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:126$6_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1007' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:127$7_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1008' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:127$7_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1009' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:127$7_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1010' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:128$8_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1011' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:128$8_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1012' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:128$8_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1013' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:129$9_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1014' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:129$9_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1015' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:129$9_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1016' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:130$10_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1017' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:130$10_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1018' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:130$10_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1019' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:131$11_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1020' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:131$11_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1021' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:131$11_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1022' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:132$12_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1023' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:132$12_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1024' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:132$12_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1025' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:133$13_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1026' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:133$13_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1027' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:133$13_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1028' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:134$14_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1029' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:134$14_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1030' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:134$14_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1031' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:135$15_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1032' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:135$15_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1033' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:135$15_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1034' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:136$16_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1035' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:136$16_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1036' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:136$16_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1037' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:137$17_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1038' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:137$17_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1039' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:137$17_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1040' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:138$18_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1041' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:138$18_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1042' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:138$18_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1043' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:139$19_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1044' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:139$19_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1045' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:139$19_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1046' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:140$20_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1047' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:140$20_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1048' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:140$20_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1049' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:141$21_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1050' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:141$21_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1051' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:141$21_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1052' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:142$22_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1053' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:142$22_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1054' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:142$22_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1055' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:143$23_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1056' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:143$23_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1057' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:143$23_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1058' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:144$24_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1059' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:144$24_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1060' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:144$24_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1061' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:145$25_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1062' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:145$25_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1063' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:145$25_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1064' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:306$26_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1065' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:306$26_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1066' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:306$26_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1067' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:307$27_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1068' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:307$27_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1069' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:307$27_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1070' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:308$28_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1071' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:308$28_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1072' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:308$28_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1073' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:309$29_ADDR' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1074' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:309$29_DATA' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1075' with positive edge clock. Creating register for signal `\top.$memwr$\sq_figure$example.v:309$29_EN' using process `\top.$proc$example.v:110$39'. created $dff cell `$procdff$1076' with positive edge clock. Creating register for signal `\top.\clk_div' using process `\top.$proc$example.v:46$30'. created $dff cell `$procdff$1077' with positive edge clock. 2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$proc$example.v:96$224'. Removing empty process `top.$proc$example.v:95$223'. Removing empty process `top.$proc$example.v:94$222'. Removing empty process `top.$proc$example.v:93$221'. Removing empty process `top.$proc$example.v:63$220'. Removing empty process `top.$proc$example.v:62$219'. Found and cleaned up 34 empty switches in `\top.$proc$example.v:110$39'. Removing empty process `top.$proc$example.v:110$39'. Removing empty process `top.$proc$example.v:46$30'. Cleaned up 34 empty switches. 2.4. Executing FLATTEN pass (flatten design). No more expansions possible. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing SYNTH pass. 2.7.1. Executing PROC pass (convert processes to netlists). 2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.7.1.3. Executing PROC_INIT pass (extract init attributes). 2.7.1.4. Executing PROC_ARST pass (detect async resets in processes). 2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs). 2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.7.2. Executing OPT_EXPR pass (perform const folding). Replacing $eq cell `$eq$example.v:123$119' (1) in module `\top' with constant driver `$eq$example.v:123$119_Y = \reset'. Replacing $eq cell `$eq$example.v:192$135' (1) in module `\top' with constant driver `$eq$example.v:192$135_Y = \disp_en'. Replacing $eq cell `$eq$example.v:192$136' in module `top' with inverter. Replacing $eq cell `$eq$example.v:193$139' in module `top' with $logic_not. Replacing $eq cell `$eq$example.v:193$140' in module `top' with $logic_not. Replacing $eq cell `$eq$example.v:202$157' (1) in module `\top' with constant driver `$eq$example.v:202$157_Y = $shiftx$example.v:202$156_Y'. Replacing $eq cell `$eq$example.v:269$169' (1) in module `\top' with constant driver `$eq$example.v:269$169_Y = \ps2_clk_pos'. Replacing $eq cell `$eq$example.v:304$173' in module `top' with $logic_not. Replacing $eq cell `$eq$example.v:314$188' (1) in module `\top' with constant driver `$eq$example.v:314$188_Y = \u_arr'. Replacing $eq cell `$eq$example.v:327$190' (1) in module `\top' with constant driver `$eq$example.v:327$190_Y = \l_arr'. Replacing $eq cell `$eq$example.v:340$192' (1) in module `\top' with constant driver `$eq$example.v:340$192_Y = \d_arr'. Replacing $eq cell `$eq$example.v:353$194' (1) in module `\top' with constant driver `$eq$example.v:353$194_Y = \r_arr'. 2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$mux' cell `$procmux$250'. removing unused `$mux' cell `$procmux$253'. removing unused `$mux' cell `$procmux$256'. removing unused `$mux' cell `$procmux$283'. removing unused `$mux' cell `$procmux$431'. removing unused `$mux' cell `$procmux$433'. removing unused `$mux' cell `$procmux$436'. removing unused `$mux' cell `$procmux$831'. removing unused `$mux' cell `$procmux$833'. removing unused `$mux' cell `$procmux$843'. removing unused `$mux' cell `$procmux$846'. removing unused `$mux' cell `$procmux$848'. removing unused `$mux' cell `$procmux$893'. removing unused `$mux' cell `$procmux$932'. removing unused `$mux' cell `$procmux$938'. removing unused `$dff' cell `$procdff$992'. removing unused `$dff' cell `$procdff$1000'. removing unused `$dff' cell `$procdff$1001'. removing unused `$dff' cell `$procdff$1002'. removing unused `$dff' cell `$procdff$1003'. removing unused `$dff' cell `$procdff$1004'. removing unused non-port wire \ps2_data_reg_prev1. removed 394 unused temporary wires. Removed 21 unused cells and 394 unused wires. 2.7.4. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.7.5. Executing OPT pass (performing simple optimizations). 2.7.5.1. Executing OPT_EXPR pass (perform const folding). 2.7.5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$lt$example.v:186$132' is identical to cell `$lt$example.v:180$130'. Redirecting output \Y: $lt$example.v:186$132_Y = $lt$example.v:180$130_Y Removing $lt cell `$lt$example.v:186$132' from module `\top'. Cell `$lt$example.v:186$133' is identical to cell `$lt$example.v:183$131'. Redirecting output \Y: $lt$example.v:186$133_Y = $lt$example.v:183$131_Y Removing $lt cell `$lt$example.v:186$133' from module `\top'. Removed a total of 2 cells. 2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$229 Root of a mux tree: $procmux$247 (pure) Root of a mux tree: $procmux$262 Root of a mux tree: $procmux$280 (pure) Root of a mux tree: $procmux$289 Root of a mux tree: $procmux$307 (pure) Root of a mux tree: $procmux$313 Root of a mux tree: $procmux$331 (pure) Root of a mux tree: $procmux$337 Root of a mux tree: $procmux$355 (pure) Root of a mux tree: $procmux$361 Root of a mux tree: $procmux$379 (pure) Root of a mux tree: $procmux$385 Root of a mux tree: $procmux$403 (pure) Root of a mux tree: $procmux$409 Root of a mux tree: $procmux$427 (pure) Root of a mux tree: $procmux$439 (pure) Root of a mux tree: $procmux$442 (pure) Root of a mux tree: $procmux$445 (pure) Root of a mux tree: $procmux$448 (pure) Root of a mux tree: $procmux$451 (pure) Root of a mux tree: $procmux$454 (pure) Root of a mux tree: $procmux$457 (pure) Root of a mux tree: $procmux$460 (pure) Root of a mux tree: $procmux$463 (pure) Root of a mux tree: $procmux$466 (pure) Root of a mux tree: $procmux$469 (pure) Root of a mux tree: $procmux$472 (pure) Root of a mux tree: $procmux$475 (pure) Root of a mux tree: $procmux$478 (pure) Root of a mux tree: $procmux$481 (pure) Root of a mux tree: $procmux$484 (pure) Root of a mux tree: $procmux$487 (pure) Root of a mux tree: $procmux$490 (pure) Root of a mux tree: $procmux$493 (pure) Root of a mux tree: $procmux$496 (pure) Root of a mux tree: $procmux$499 (pure) Root of a mux tree: $procmux$502 (pure) Root of a mux tree: $procmux$505 (pure) Root of a mux tree: $procmux$508 (pure) Root of a mux tree: $procmux$511 (pure) Root of a mux tree: $procmux$514 (pure) Root of a mux tree: $procmux$517 (pure) Root of a mux tree: $procmux$520 (pure) Root of a mux tree: $procmux$523 (pure) Root of a mux tree: $procmux$526 (pure) Root of a mux tree: $procmux$529 (pure) Root of a mux tree: $procmux$532 (pure) Root of a mux tree: $procmux$535 (pure) Root of a mux tree: $procmux$538 (pure) Root of a mux tree: $procmux$541 (pure) Root of a mux tree: $procmux$544 (pure) Root of a mux tree: $procmux$547 (pure) Root of a mux tree: $procmux$550 (pure) Root of a mux tree: $procmux$553 (pure) Root of a mux tree: $procmux$556 (pure) Root of a mux tree: $procmux$559 (pure) Root of a mux tree: $procmux$562 (pure) Root of a mux tree: $procmux$565 (pure) Root of a mux tree: $procmux$568 (pure) Root of a mux tree: $procmux$571 (pure) Root of a mux tree: $procmux$574 (pure) Root of a mux tree: $procmux$577 (pure) Root of a mux tree: $procmux$580 (pure) Root of a mux tree: $procmux$583 (pure) Root of a mux tree: $procmux$586 (pure) Root of a mux tree: $procmux$589 (pure) Root of a mux tree: $procmux$592 (pure) Root of a mux tree: $procmux$595 (pure) Root of a mux tree: $procmux$598 (pure) Root of a mux tree: $procmux$601 (pure) Root of a mux tree: $procmux$604 (pure) Root of a mux tree: $procmux$607 (pure) Root of a mux tree: $procmux$610 (pure) Root of a mux tree: $procmux$613 (pure) Root of a mux tree: $procmux$616 (pure) Root of a mux tree: $procmux$619 (pure) Root of a mux tree: $procmux$622 (pure) Root of a mux tree: $procmux$625 (pure) Root of a mux tree: $procmux$628 (pure) Root of a mux tree: $procmux$631 (pure) Root of a mux tree: $procmux$634 (pure) Root of a mux tree: $procmux$637 (pure) Root of a mux tree: $procmux$640 (pure) Root of a mux tree: $procmux$643 (pure) Root of a mux tree: $procmux$646 (pure) Root of a mux tree: $procmux$649 (pure) Root of a mux tree: $procmux$652 (pure) Root of a mux tree: $procmux$659 Root of a mux tree: $procmux$667 Root of a mux tree: $procmux$680 Root of a mux tree: $procmux$695 (pure) Root of a mux tree: $procmux$702 Root of a mux tree: $procmux$710 Root of a mux tree: $procmux$717 Root of a mux tree: $procmux$728 Root of a mux tree: $procmux$738 (pure) Removing pure flag from root mux $procmux$702. Root of a mux tree: $procmux$745 Replacing known input bits on port A of cell $procmux$745: \l_arr -> 1'0 Replacing known input bits on port B of cell $procmux$743: \l_arr -> 1'1 Root of a mux tree: $procmux$753 Root of a mux tree: $procmux$766 Root of a mux tree: $procmux$781 (pure) Root of a mux tree: $procmux$788 Replacing known input bits on port A of cell $procmux$788: \u_arr -> 1'0 Replacing known input bits on port B of cell $procmux$786: \u_arr -> 1'1 Root of a mux tree: $procmux$796 Root of a mux tree: $procmux$803 Root of a mux tree: $procmux$814 Root of a mux tree: $procmux$824 (pure) Removing pure flag from root mux $procmux$788. Root of a mux tree: $procmux$827 (pure) Root of a mux tree: $procmux$839 (pure) Root of a mux tree: $procmux$854 (pure) Root of a mux tree: $procmux$857 Root of a mux tree: $procmux$864 Root of a mux tree: $procmux$872 (pure) Root of a mux tree: $procmux$875 Root of a mux tree: $procmux$882 Root of a mux tree: $procmux$890 (pure) Root of a mux tree: $procmux$896 (pure) Root of a mux tree: $procmux$905 (pure) Root of a mux tree: $procmux$911 (pure) Root of a mux tree: $procmux$917 (pure) Root of a mux tree: $procmux$923 (pure) Root of a mux tree: $procmux$926 (pure) Root of a mux tree: $procmux$929 (pure) Root of a mux tree: $procmux$935 (pure) Root of a mux tree: $procmux$941 (pure) Root of a mux tree: $procmux$953 (pure) Root of a mux tree: $procmux$973 (pure) Root of a mux tree: $procmux$788 (rerun as non-pure) Root of a mux tree: $procmux$702 (rerun as non-pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$439: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] New connections: $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [19:1] = { $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] } Consolidated identical input bits for $mux cell $procmux$448: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] New connections: $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [19:1] = { $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] } Consolidated identical input bits for $mux cell $procmux$457: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] New connections: $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [19:1] = { $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] } Consolidated identical input bits for $mux cell $procmux$466: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] New connections: $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [19:1] = { $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] } Consolidated identical input bits for $mux cell $procmux$475: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] New connections: $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [19:1] = { $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] } Consolidated identical input bits for $mux cell $procmux$484: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] New connections: $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [19:1] = { $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] } Consolidated identical input bits for $mux cell $procmux$493: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] New connections: $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [19:1] = { $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] } Consolidated identical input bits for $mux cell $procmux$502: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] New connections: $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [19:1] = { $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] } Consolidated identical input bits for $mux cell $procmux$511: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] New connections: $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [19:1] = { $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] } Consolidated identical input bits for $mux cell $procmux$520: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] New connections: $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [19:1] = { $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] } Consolidated identical input bits for $mux cell $procmux$529: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] New connections: $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [19:1] = { $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] } Consolidated identical input bits for $mux cell $procmux$538: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] New connections: $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [19:1] = { $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] } Consolidated identical input bits for $mux cell $procmux$547: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] New connections: $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [19:1] = { $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] } Consolidated identical input bits for $mux cell $procmux$556: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] New connections: $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [19:1] = { $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] } Consolidated identical input bits for $mux cell $procmux$565: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] New connections: $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [19:1] = { $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] } Consolidated identical input bits for $mux cell $procmux$574: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] New connections: $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [19:1] = { $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] } Consolidated identical input bits for $mux cell $procmux$583: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] New connections: $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [19:1] = { $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] } Consolidated identical input bits for $mux cell $procmux$592: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] New connections: $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [19:1] = { $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] } Consolidated identical input bits for $mux cell $procmux$601: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] New connections: $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [19:1] = { $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] } Consolidated identical input bits for $mux cell $procmux$610: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] New connections: $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [19:1] = { $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] } Consolidated identical input bits for $mux cell $procmux$619: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] New connections: $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [19:1] = { $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] } Consolidated identical input bits for $mux cell $procmux$628: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] New connections: $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [19:1] = { $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] } Consolidated identical input bits for $mux cell $procmux$637: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] New connections: $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [19:1] = { $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] } Consolidated identical input bits for $mux cell $procmux$646: Old ports: A=20'00000000000000000000, B=20'11111111111111111111, Y=$0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 New ports: A=1'0, B=1'1, Y=$0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] New connections: $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [19:1] = { $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] } Optimizing cells in module \top. Performed a total of 24 changes. 2.7.5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$procmux$448' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:127$7_EN[19:0]$50 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$448' from module `\top'. Cell `$procmux$457' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:128$8_EN[19:0]$53 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$457' from module `\top'. Cell `$procmux$466' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:129$9_EN[19:0]$56 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$466' from module `\top'. Cell `$procmux$475' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:130$10_EN[19:0]$59 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$475' from module `\top'. Cell `$procmux$484' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:131$11_EN[19:0]$62 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$484' from module `\top'. Cell `$procmux$487' is identical to cell `$procmux$478'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:131$11_DATA[19:0]$61 = $0$memwr$\sq_figure$example.v:130$10_DATA[19:0]$58 Removing $mux cell `$procmux$487' from module `\top'. Cell `$procmux$493' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:132$12_EN[19:0]$65 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$493' from module `\top'. Cell `$procmux$502' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:133$13_EN[19:0]$68 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$502' from module `\top'. Cell `$procmux$505' is identical to cell `$procmux$496'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:133$13_DATA[19:0]$67 = $0$memwr$\sq_figure$example.v:132$12_DATA[19:0]$64 Removing $mux cell `$procmux$505' from module `\top'. Cell `$procmux$511' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:134$14_EN[19:0]$71 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$511' from module `\top'. Cell `$procmux$520' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:135$15_EN[19:0]$74 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$520' from module `\top'. Cell `$procmux$523' is identical to cell `$procmux$514'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:135$15_DATA[19:0]$73 = $0$memwr$\sq_figure$example.v:134$14_DATA[19:0]$70 Removing $mux cell `$procmux$523' from module `\top'. Cell `$procmux$529' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:136$16_EN[19:0]$77 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$529' from module `\top'. Cell `$procmux$532' is identical to cell `$procmux$514'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:136$16_DATA[19:0]$76 = $0$memwr$\sq_figure$example.v:134$14_DATA[19:0]$70 Removing $mux cell `$procmux$532' from module `\top'. Cell `$procmux$538' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:137$17_EN[19:0]$80 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$538' from module `\top'. Cell `$procmux$541' is identical to cell `$procmux$514'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:137$17_DATA[19:0]$79 = $0$memwr$\sq_figure$example.v:134$14_DATA[19:0]$70 Removing $mux cell `$procmux$541' from module `\top'. Cell `$procmux$547' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:138$18_EN[19:0]$83 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$547' from module `\top'. Cell `$procmux$550' is identical to cell `$procmux$514'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:138$18_DATA[19:0]$82 = $0$memwr$\sq_figure$example.v:134$14_DATA[19:0]$70 Removing $mux cell `$procmux$550' from module `\top'. Cell `$procmux$556' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:139$19_EN[19:0]$86 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$556' from module `\top'. Cell `$procmux$559' is identical to cell `$procmux$496'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:139$19_DATA[19:0]$85 = $0$memwr$\sq_figure$example.v:132$12_DATA[19:0]$64 Removing $mux cell `$procmux$559' from module `\top'. Cell `$procmux$565' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:140$20_EN[19:0]$89 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$565' from module `\top'. Cell `$procmux$568' is identical to cell `$procmux$496'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:140$20_DATA[19:0]$88 = $0$memwr$\sq_figure$example.v:132$12_DATA[19:0]$64 Removing $mux cell `$procmux$568' from module `\top'. Cell `$procmux$574' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:141$21_EN[19:0]$92 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$574' from module `\top'. Cell `$procmux$577' is identical to cell `$procmux$478'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:141$21_DATA[19:0]$91 = $0$memwr$\sq_figure$example.v:130$10_DATA[19:0]$58 Removing $mux cell `$procmux$577' from module `\top'. Cell `$procmux$583' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:142$22_EN[19:0]$95 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$583' from module `\top'. Cell `$procmux$586' is identical to cell `$procmux$478'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:142$22_DATA[19:0]$94 = $0$memwr$\sq_figure$example.v:130$10_DATA[19:0]$58 Removing $mux cell `$procmux$586' from module `\top'. Cell `$procmux$592' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:143$23_EN[19:0]$98 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$592' from module `\top'. Cell `$procmux$595' is identical to cell `$procmux$469'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:143$23_DATA[19:0]$97 = $0$memwr$\sq_figure$example.v:129$9_DATA[19:0]$55 Removing $mux cell `$procmux$595' from module `\top'. Cell `$procmux$601' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:144$24_EN[19:0]$101 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$601' from module `\top'. Cell `$procmux$604' is identical to cell `$procmux$460'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:144$24_DATA[19:0]$100 = $0$memwr$\sq_figure$example.v:128$8_DATA[19:0]$52 Removing $mux cell `$procmux$604' from module `\top'. Cell `$procmux$610' is identical to cell `$procmux$439'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:145$25_EN[19:0]$104 [0] = $0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [0] Removing $mux cell `$procmux$610' from module `\top'. Cell `$procmux$613' is identical to cell `$procmux$451'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:145$25_DATA[19:0]$103 = $0$memwr$\sq_figure$example.v:127$7_DATA[19:0]$49 Removing $mux cell `$procmux$613' from module `\top'. Cell `$procmux$628' is identical to cell `$procmux$619'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:307$27_EN[19:0]$110 [0] = $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] Removing $mux cell `$procmux$628' from module `\top'. Cell `$procmux$637' is identical to cell `$procmux$619'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:308$28_EN[19:0]$113 [0] = $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] Removing $mux cell `$procmux$637' from module `\top'. Cell `$procmux$646' is identical to cell `$procmux$619'. Redirecting output \Y: $0$memwr$\sq_figure$example.v:309$29_EN[19:0]$116 [0] = $0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [0] Removing $mux cell `$procmux$646' from module `\top'. Cell `$procmux$966' is identical to cell `$procmux$946'. Redirecting output \Y: $procmux$966_Y = $procmux$946_Y Removing $mux cell `$procmux$966' from module `\top'. Cell `$procmux$968' is identical to cell `$procmux$948'. Redirecting output \Y: $procmux$968_Y = $procmux$948_Y Removing $mux cell `$procmux$968' from module `\top'. Cell `$procdff$1010' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:127$7_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1010' from module `\top'. Cell `$procdff$1013' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:128$8_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1013' from module `\top'. Cell `$procdff$1016' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:129$9_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1016' from module `\top'. Cell `$procdff$1019' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:130$10_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1019' from module `\top'. Cell `$procdff$1021' is identical to cell `$procdff$1018'. Redirecting output \Q: $memwr$\sq_figure$example.v:131$11_DATA = $memwr$\sq_figure$example.v:130$10_DATA Removing $dff cell `$procdff$1021' from module `\top'. Cell `$procdff$1022' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:131$11_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1022' from module `\top'. Cell `$procdff$1025' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:132$12_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1025' from module `\top'. Cell `$procdff$1027' is identical to cell `$procdff$1024'. Redirecting output \Q: $memwr$\sq_figure$example.v:133$13_DATA = $memwr$\sq_figure$example.v:132$12_DATA Removing $dff cell `$procdff$1027' from module `\top'. Cell `$procdff$1028' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:133$13_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1028' from module `\top'. Cell `$procdff$1031' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:134$14_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1031' from module `\top'. Cell `$procdff$1033' is identical to cell `$procdff$1030'. Redirecting output \Q: $memwr$\sq_figure$example.v:135$15_DATA = $memwr$\sq_figure$example.v:134$14_DATA Removing $dff cell `$procdff$1033' from module `\top'. Cell `$procdff$1034' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:135$15_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1034' from module `\top'. Cell `$procdff$1036' is identical to cell `$procdff$1030'. Redirecting output \Q: $memwr$\sq_figure$example.v:136$16_DATA = $memwr$\sq_figure$example.v:134$14_DATA Removing $dff cell `$procdff$1036' from module `\top'. Cell `$procdff$1037' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:136$16_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1037' from module `\top'. Cell `$procdff$1039' is identical to cell `$procdff$1030'. Redirecting output \Q: $memwr$\sq_figure$example.v:137$17_DATA = $memwr$\sq_figure$example.v:134$14_DATA Removing $dff cell `$procdff$1039' from module `\top'. Cell `$procdff$1040' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:137$17_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1040' from module `\top'. Cell `$procdff$1042' is identical to cell `$procdff$1030'. Redirecting output \Q: $memwr$\sq_figure$example.v:138$18_DATA = $memwr$\sq_figure$example.v:134$14_DATA Removing $dff cell `$procdff$1042' from module `\top'. Cell `$procdff$1043' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:138$18_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1043' from module `\top'. Cell `$procdff$1045' is identical to cell `$procdff$1024'. Redirecting output \Q: $memwr$\sq_figure$example.v:139$19_DATA = $memwr$\sq_figure$example.v:132$12_DATA Removing $dff cell `$procdff$1045' from module `\top'. Cell `$procdff$1046' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:139$19_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1046' from module `\top'. Cell `$procdff$1048' is identical to cell `$procdff$1024'. Redirecting output \Q: $memwr$\sq_figure$example.v:140$20_DATA = $memwr$\sq_figure$example.v:132$12_DATA Removing $dff cell `$procdff$1048' from module `\top'. Cell `$procdff$1049' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:140$20_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1049' from module `\top'. Cell `$procdff$1051' is identical to cell `$procdff$1018'. Redirecting output \Q: $memwr$\sq_figure$example.v:141$21_DATA = $memwr$\sq_figure$example.v:130$10_DATA Removing $dff cell `$procdff$1051' from module `\top'. Cell `$procdff$1052' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:141$21_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1052' from module `\top'. Cell `$procdff$1054' is identical to cell `$procdff$1018'. Redirecting output \Q: $memwr$\sq_figure$example.v:142$22_DATA = $memwr$\sq_figure$example.v:130$10_DATA Removing $dff cell `$procdff$1054' from module `\top'. Cell `$procdff$1055' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:142$22_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1055' from module `\top'. Cell `$procdff$1057' is identical to cell `$procdff$1015'. Redirecting output \Q: $memwr$\sq_figure$example.v:143$23_DATA = $memwr$\sq_figure$example.v:129$9_DATA Removing $dff cell `$procdff$1057' from module `\top'. Cell `$procdff$1058' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:143$23_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1058' from module `\top'. Cell `$procdff$1060' is identical to cell `$procdff$1012'. Redirecting output \Q: $memwr$\sq_figure$example.v:144$24_DATA = $memwr$\sq_figure$example.v:128$8_DATA Removing $dff cell `$procdff$1060' from module `\top'. Cell `$procdff$1061' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:144$24_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1061' from module `\top'. Cell `$procdff$1063' is identical to cell `$procdff$1009'. Redirecting output \Q: $memwr$\sq_figure$example.v:145$25_DATA = $memwr$\sq_figure$example.v:127$7_DATA Removing $dff cell `$procdff$1063' from module `\top'. Cell `$procdff$1064' is identical to cell `$procdff$1007'. Redirecting output \Q: $memwr$\sq_figure$example.v:145$25_EN = $memwr$\sq_figure$example.v:126$6_EN Removing $dff cell `$procdff$1064' from module `\top'. Cell `$procdff$1070' is identical to cell `$procdff$1067'. Redirecting output \Q: $memwr$\sq_figure$example.v:307$27_EN = $memwr$\sq_figure$example.v:306$26_EN Removing $dff cell `$procdff$1070' from module `\top'. Cell `$procdff$1073' is identical to cell `$procdff$1067'. Redirecting output \Q: $memwr$\sq_figure$example.v:308$28_EN = $memwr$\sq_figure$example.v:306$26_EN Removing $dff cell `$procdff$1073' from module `\top'. Cell `$procdff$1076' is identical to cell `$procdff$1067'. Redirecting output \Q: $memwr$\sq_figure$example.v:309$29_EN = $memwr$\sq_figure$example.v:306$26_EN Removing $dff cell `$procdff$1076' from module `\top'. Removed a total of 72 cells. 2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values). Removing $procdff$976 ($dff) from module top. Replaced 1 DFF cells. 2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused non-port wire \vga_g_r. removed 75 unused temporary wires. Removed 21 unused cells and 469 unused wires. 2.7.5.8. Executing OPT_EXPR pass (perform const folding). 2.7.5.9. Rerunning OPT passes. (Maybe there is more to do..) 2.7.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$229 Root of a mux tree: $procmux$247 (pure) Root of a mux tree: $procmux$262 Root of a mux tree: $procmux$280 (pure) Root of a mux tree: $procmux$289 Root of a mux tree: $procmux$307 (pure) Root of a mux tree: $procmux$313 Root of a mux tree: $procmux$331 (pure) Root of a mux tree: $procmux$337 Root of a mux tree: $procmux$355 (pure) Root of a mux tree: $procmux$361 Root of a mux tree: $procmux$379 (pure) Root of a mux tree: $procmux$385 Root of a mux tree: $procmux$403 (pure) Root of a mux tree: $procmux$409 Root of a mux tree: $procmux$427 (pure) Root of a mux tree: $procmux$439 (pure) Root of a mux tree: $procmux$442 (pure) Root of a mux tree: $procmux$445 (pure) Root of a mux tree: $procmux$451 (pure) Root of a mux tree: $procmux$454 (pure) Root of a mux tree: $procmux$460 (pure) Root of a mux tree: $procmux$463 (pure) Root of a mux tree: $procmux$469 (pure) Root of a mux tree: $procmux$472 (pure) Root of a mux tree: $procmux$478 (pure) Root of a mux tree: $procmux$481 (pure) Root of a mux tree: $procmux$490 (pure) Root of a mux tree: $procmux$496 (pure) Root of a mux tree: $procmux$499 (pure) Root of a mux tree: $procmux$508 (pure) Root of a mux tree: $procmux$514 (pure) Root of a mux tree: $procmux$517 (pure) Root of a mux tree: $procmux$526 (pure) Root of a mux tree: $procmux$535 (pure) Root of a mux tree: $procmux$544 (pure) Root of a mux tree: $procmux$553 (pure) Root of a mux tree: $procmux$562 (pure) Root of a mux tree: $procmux$571 (pure) Root of a mux tree: $procmux$580 (pure) Root of a mux tree: $procmux$589 (pure) Root of a mux tree: $procmux$598 (pure) Root of a mux tree: $procmux$607 (pure) Root of a mux tree: $procmux$616 (pure) Root of a mux tree: $procmux$619 (pure) Root of a mux tree: $procmux$622 (pure) Root of a mux tree: $procmux$625 (pure) Root of a mux tree: $procmux$631 (pure) Root of a mux tree: $procmux$634 (pure) Root of a mux tree: $procmux$640 (pure) Root of a mux tree: $procmux$643 (pure) Root of a mux tree: $procmux$649 (pure) Root of a mux tree: $procmux$652 (pure) Root of a mux tree: $procmux$659 Root of a mux tree: $procmux$667 Root of a mux tree: $procmux$680 Root of a mux tree: $procmux$695 (pure) Root of a mux tree: $procmux$702 Root of a mux tree: $procmux$710 Root of a mux tree: $procmux$717 Root of a mux tree: $procmux$728 Root of a mux tree: $procmux$738 (pure) Removing pure flag from root mux $procmux$702. Root of a mux tree: $procmux$745 Root of a mux tree: $procmux$753 Root of a mux tree: $procmux$766 Root of a mux tree: $procmux$781 (pure) Root of a mux tree: $procmux$788 Root of a mux tree: $procmux$796 Root of a mux tree: $procmux$803 Root of a mux tree: $procmux$814 Root of a mux tree: $procmux$824 (pure) Removing pure flag from root mux $procmux$788. Root of a mux tree: $procmux$827 (pure) Root of a mux tree: $procmux$839 (pure) Root of a mux tree: $procmux$854 (pure) Root of a mux tree: $procmux$857 Root of a mux tree: $procmux$864 Root of a mux tree: $procmux$872 (pure) Root of a mux tree: $procmux$875 Root of a mux tree: $procmux$882 Root of a mux tree: $procmux$890 (pure) Root of a mux tree: $procmux$896 (pure) Root of a mux tree: $procmux$905 (pure) Root of a mux tree: $procmux$911 (pure) Root of a mux tree: $procmux$917 (pure) Root of a mux tree: $procmux$923 (pure) Root of a mux tree: $procmux$926 (pure) Root of a mux tree: $procmux$929 (pure) Root of a mux tree: $procmux$935 (pure) Root of a mux tree: $procmux$941 (pure) Root of a mux tree: $procmux$948 Root of a mux tree: $procmux$953 (pure) Root of a mux tree: $procmux$973 (pure) Root of a mux tree: $procmux$788 (rerun as non-pure) Root of a mux tree: $procmux$702 (rerun as non-pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.7.5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.5.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 21 unused cells and 469 unused wires. 2.7.5.15. Executing OPT_EXPR pass (perform const folding). 2.7.5.16. Finished OPT passes. (There is nothing left to do.) 2.7.6. Executing WREDUCE pass (reducing word size of cells). Removed top 27 address bits (of 32) from memory read port top.$memrd$\sq_figure$example.v:306$178 (sq_figure). Removed top 27 address bits (of 32) from memory read port top.$memrd$\sq_figure$example.v:307$180 (sq_figure). Removed top 27 address bits (of 32) from memory read port top.$memrd$\sq_figure$example.v:308$182 (sq_figure). Removed top 27 address bits (of 32) from memory read port top.$memrd$\sq_figure$example.v:309$184 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:126$195 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:127$196 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:128$197 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:129$198 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:130$199 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:131$200 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:132$201 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:133$202 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:134$203 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:135$204 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:136$205 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:137$206 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:138$207 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:139$208 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:140$209 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:141$210 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:142$211 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:143$212 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:144$213 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:145$214 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:306$215 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:307$216 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:308$217 (sq_figure). Removed top 27 address bits (of 32) from memory write port top.$memwr$\sq_figure$example.v:309$218 (sq_figure). Removed top 1 bits (of 2) from port B of cell top.$add$example.v:47$31 ($add). Removed top 28 bits (of 32) from port B of cell top.$sub$example.v:79$32 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:79$32 ($sub). Removed top 28 bits (of 32) from port B of cell top.$add$example.v:80$33 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:80$33 ($add). Removed top 28 bits (of 32) from port B of cell top.$sub$example.v:81$34 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:81$34 ($sub). Removed top 28 bits (of 32) from port B of cell top.$add$example.v:82$35 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:82$35 ($add). Removed top 5 bits (of 10) from port Y of cell top.$sub$example.v:105$36 ($sub). Removed top 5 bits (of 10) from port A of cell top.$sub$example.v:105$36 ($sub). Removed top 5 bits (of 10) from port B of cell top.$sub$example.v:105$36 ($sub). Removed top 5 bits (of 10) from port Y of cell top.$sub$example.v:106$37 ($sub). Removed top 5 bits (of 10) from port A of cell top.$sub$example.v:106$37 ($sub). Removed top 5 bits (of 10) from port B of cell top.$sub$example.v:106$37 ($sub). Removed top 1 bits (of 2) from port B of cell top.$eq$example.v:108$38 ($eq). Removed top 24 bits (of 32) from port B of cell top.$gt$example.v:112$117 ($gt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:117$118 ($add). Removed top 24 bits (of 32) from port Y of cell top.$add$example.v:117$118 ($add). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:155$120 ($lt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:156$121 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:156$121 ($add). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:160$122 ($lt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:161$123 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:161$123 ($add). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:168$124 ($lt). Removed top 22 bits (of 32) from port B of cell top.$gt$example.v:168$125 ($gt). Removed top 23 bits (of 32) from port B of cell top.$lt$example.v:174$127 ($lt). Removed top 23 bits (of 32) from port B of cell top.$gt$example.v:174$128 ($gt). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:180$130 ($lt). Removed top 23 bits (of 32) from port B of cell top.$lt$example.v:183$131 ($lt). Removed top 1 bits (of 10) from port B of cell top.$eq$example.v:193$142 ($eq). Removed top 9 bits (of 10) from port B of cell top.$eq$example.v:225$158 ($eq). Removed top 9 bits (of 10) from port B of cell top.$eq$example.v:225$159 ($eq). Removed top 28 bits (of 32) from port B of cell top.$gt$example.v:227$161 ($gt). Removed top 31 bits (of 32) from port B of cell top.$sub$example.v:228$162 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:228$162 ($sub). Removed top 23 bits (of 32) from port B of cell top.$lt$example.v:237$163 ($lt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:238$164 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:238$164 ($add). Removed top 28 bits (of 32) from port B of cell top.$gt$example.v:247$165 ($gt). Removed top 31 bits (of 32) from port B of cell top.$sub$example.v:248$166 ($sub). Removed top 22 bits (of 32) from port Y of cell top.$sub$example.v:248$166 ($sub). Removed top 22 bits (of 32) from port B of cell top.$lt$example.v:257$167 ($lt). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:258$168 ($add). Removed top 22 bits (of 32) from port Y of cell top.$add$example.v:258$168 ($add). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:270$170 ($add). Removed top 28 bits (of 32) from port Y of cell top.$add$example.v:270$170 ($add). Removed top 31 bits (of 32) from port B of cell top.$add$example.v:302$172 ($add). Removed top 11 bits (of 32) from port Y of cell top.$add$example.v:302$172 ($add). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:306$179 ($xor). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:307$181 ($xor). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:308$183 ($xor). Removed top 7 bits (of 20) from port B of cell top.$xor$example.v:309$185 ($xor). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:313$187 ($eq). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:326$189 ($eq). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:339$191 ($eq). Removed top 1 bits (of 8) from port B of cell top.$eq$example.v:352$193 ($eq). Removed cell top.$procmux$442 ($mux). Removed cell top.$procmux$445 ($mux). Removed cell top.$procmux$451 ($mux). Removed cell top.$procmux$454 ($mux). Removed cell top.$procmux$460 ($mux). Removed cell top.$procmux$463 ($mux). Removed cell top.$procmux$469 ($mux). Removed cell top.$procmux$472 ($mux). Removed cell top.$procmux$478 ($mux). Removed cell top.$procmux$481 ($mux). Removed cell top.$procmux$490 ($mux). Removed cell top.$procmux$496 ($mux). Removed cell top.$procmux$499 ($mux). Removed cell top.$procmux$508 ($mux). Removed cell top.$procmux$514 ($mux). Removed cell top.$procmux$517 ($mux). Removed cell top.$procmux$526 ($mux). Removed cell top.$procmux$535 ($mux). Removed cell top.$procmux$544 ($mux). Removed cell top.$procmux$553 ($mux). Removed cell top.$procmux$562 ($mux). Removed cell top.$procmux$571 ($mux). Removed cell top.$procmux$580 ($mux). Removed cell top.$procmux$589 ($mux). Removed cell top.$procmux$598 ($mux). Removed cell top.$procmux$607 ($mux). Removed cell top.$procmux$616 ($mux). Removed cell top.$procmux$622 ($mux). Removed cell top.$procmux$625 ($mux). Removed cell top.$procmux$631 ($mux). Removed cell top.$procmux$634 ($mux). Removed cell top.$procmux$640 ($mux). Removed cell top.$procmux$643 ($mux). Removed cell top.$procmux$649 ($mux). Removed cell top.$procmux$652 ($mux). Removed top 24 bits (of 32) from wire top.$add$example.v:117$118_Y. Removed top 22 bits (of 32) from wire top.$add$example.v:161$123_Y. Removed top 22 bits (of 32) from wire top.$add$example.v:238$164_Y. Removed top 22 bits (of 32) from wire top.$sub$example.v:228$162_Y. 2.7.7. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $add$example.v:117$118 ($add). creating $macc model for $add$example.v:156$121 ($add). creating $macc model for $add$example.v:161$123 ($add). creating $macc model for $add$example.v:238$164 ($add). creating $macc model for $add$example.v:258$168 ($add). creating $macc model for $add$example.v:270$170 ($add). creating $macc model for $add$example.v:302$172 ($add). creating $macc model for $add$example.v:47$31 ($add). creating $macc model for $add$example.v:80$33 ($add). creating $macc model for $add$example.v:82$35 ($add). creating $macc model for $sub$example.v:105$36 ($sub). creating $macc model for $sub$example.v:106$37 ($sub). creating $macc model for $sub$example.v:228$162 ($sub). creating $macc model for $sub$example.v:248$166 ($sub). creating $macc model for $sub$example.v:79$32 ($sub). creating $macc model for $sub$example.v:81$34 ($sub). creating $alu model for $macc $sub$example.v:81$34. creating $alu model for $macc $sub$example.v:79$32. creating $alu model for $macc $sub$example.v:248$166. creating $alu model for $macc $sub$example.v:228$162. creating $alu model for $macc $sub$example.v:106$37. creating $alu model for $macc $sub$example.v:105$36. creating $alu model for $macc $add$example.v:82$35. creating $alu model for $macc $add$example.v:80$33. creating $alu model for $macc $add$example.v:47$31. creating $alu model for $macc $add$example.v:302$172. creating $alu model for $macc $add$example.v:270$170. creating $alu model for $macc $add$example.v:258$168. creating $alu model for $macc $add$example.v:238$164. creating $alu model for $macc $add$example.v:161$123. creating $alu model for $macc $add$example.v:156$121. creating $alu model for $macc $add$example.v:117$118. creating $alu model for $lt$example.v:155$120 ($lt): new $alu creating $alu model for $lt$example.v:160$122 ($lt): new $alu creating $alu model for $lt$example.v:168$124 ($lt): new $alu creating $alu model for $lt$example.v:174$127 ($lt): new $alu creating $alu model for $lt$example.v:180$130 ($lt): new $alu creating $alu model for $lt$example.v:183$131 ($lt): new $alu creating $alu model for $lt$example.v:198$148 ($lt): new $alu creating $alu model for $lt$example.v:198$152 ($lt): new $alu creating $alu model for $lt$example.v:237$163 ($lt): new $alu creating $alu model for $lt$example.v:257$167 ($lt): new $alu creating $alu model for $gt$example.v:112$117 ($gt): new $alu creating $alu model for $gt$example.v:168$125 ($gt): new $alu creating $alu model for $gt$example.v:174$128 ($gt): new $alu creating $alu model for $gt$example.v:198$147 ($gt): new $alu creating $alu model for $gt$example.v:198$150 ($gt): new $alu creating $alu model for $gt$example.v:227$161 ($gt): new $alu creating $alu model for $gt$example.v:247$165 ($gt): new $alu creating $alu cell for $gt$example.v:198$150: $auto$alumacc.cc:474:replace_alu$1099 creating $alu cell for $gt$example.v:198$147: $auto$alumacc.cc:474:replace_alu$1110 creating $alu cell for $gt$example.v:174$128: $auto$alumacc.cc:474:replace_alu$1121 creating $alu cell for $gt$example.v:168$125: $auto$alumacc.cc:474:replace_alu$1126 creating $alu cell for $gt$example.v:112$117: $auto$alumacc.cc:474:replace_alu$1137 creating $alu cell for $lt$example.v:257$167: $auto$alumacc.cc:474:replace_alu$1148 creating $alu cell for $lt$example.v:237$163: $auto$alumacc.cc:474:replace_alu$1153 creating $alu cell for $lt$example.v:198$152: $auto$alumacc.cc:474:replace_alu$1164 creating $alu cell for $lt$example.v:198$148: $auto$alumacc.cc:474:replace_alu$1169 creating $alu cell for $lt$example.v:183$131: $auto$alumacc.cc:474:replace_alu$1174 creating $alu cell for $lt$example.v:180$130: $auto$alumacc.cc:474:replace_alu$1185 creating $alu cell for $lt$example.v:174$127: $auto$alumacc.cc:474:replace_alu$1190 creating $alu cell for $lt$example.v:168$124: $auto$alumacc.cc:474:replace_alu$1201 creating $alu cell for $lt$example.v:160$122: $auto$alumacc.cc:474:replace_alu$1206 creating $alu cell for $lt$example.v:155$120: $auto$alumacc.cc:474:replace_alu$1211 creating $alu cell for $add$example.v:117$118: $auto$alumacc.cc:474:replace_alu$1222 creating $alu cell for $add$example.v:156$121: $auto$alumacc.cc:474:replace_alu$1225 creating $alu cell for $add$example.v:161$123: $auto$alumacc.cc:474:replace_alu$1228 creating $alu cell for $add$example.v:238$164: $auto$alumacc.cc:474:replace_alu$1231 creating $alu cell for $add$example.v:258$168: $auto$alumacc.cc:474:replace_alu$1234 creating $alu cell for $add$example.v:270$170: $auto$alumacc.cc:474:replace_alu$1237 creating $alu cell for $add$example.v:302$172: $auto$alumacc.cc:474:replace_alu$1240 creating $alu cell for $add$example.v:47$31: $auto$alumacc.cc:474:replace_alu$1243 creating $alu cell for $gt$example.v:247$165: $auto$alumacc.cc:474:replace_alu$1246 creating $alu cell for $add$example.v:80$33: $auto$alumacc.cc:474:replace_alu$1251 creating $alu cell for $gt$example.v:227$161: $auto$alumacc.cc:474:replace_alu$1254 creating $alu cell for $add$example.v:82$35: $auto$alumacc.cc:474:replace_alu$1259 creating $alu cell for $sub$example.v:105$36: $auto$alumacc.cc:474:replace_alu$1262 creating $alu cell for $sub$example.v:106$37: $auto$alumacc.cc:474:replace_alu$1265 creating $alu cell for $sub$example.v:228$162: $auto$alumacc.cc:474:replace_alu$1268 creating $alu cell for $sub$example.v:248$166: $auto$alumacc.cc:474:replace_alu$1271 creating $alu cell for $sub$example.v:79$32: $auto$alumacc.cc:474:replace_alu$1274 creating $alu cell for $sub$example.v:81$34: $auto$alumacc.cc:474:replace_alu$1277 created 33 $alu and 0 $macc cells. 2.7.8. Executing SHARE pass (SAT-based resource sharing). 2.7.9. Executing OPT pass (performing simple optimizations). 2.7.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing away select inverter for $mux cell `$procmux$657' in module `top'. Optimizing away select inverter for $mux cell `$procmux$663' in module `top'. Optimizing away select inverter for $mux cell `$procmux$700' in module `top'. Optimizing away select inverter for $mux cell `$procmux$706' in module `top'. Optimizing away select inverter for $mux cell `$procmux$743' in module `top'. Optimizing away select inverter for $mux cell `$procmux$749' in module `top'. Optimizing away select inverter for $mux cell `$procmux$786' in module `top'. Optimizing away select inverter for $mux cell `$procmux$792' in module `top'. Optimizing away select inverter for $mux cell `$procmux$857' in module `top'. Optimizing away select inverter for $mux cell `$procmux$862' in module `top'. Optimizing away select inverter for $mux cell `$procmux$868' in module `top'. Optimizing away select inverter for $mux cell `$procmux$875' in module `top'. Optimizing away select inverter for $mux cell `$procmux$880' in module `top'. Optimizing away select inverter for $mux cell `$procmux$886' in module `top'. Optimizing away select inverter for $mux cell `$procmux$899' in module `top'. Optimizing away select inverter for $mux cell `$procmux$902' in module `top'. Optimizing away select inverter for $mux cell `$procmux$908' in module `top'. Optimizing away select inverter for $mux cell `$procmux$917' in module `top'. Optimizing away select inverter for $mux cell `$procmux$923' in module `top'. Optimizing away select inverter for $mux cell `$procmux$926' in module `top'. Optimizing away select inverter for $mux cell `$procmux$929' in module `top'. 2.7.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$procdff$1065' is identical to cell `$procdff$1029'. Redirecting output \Q: $memwr$\sq_figure$example.v:306$26_ADDR = $memwr$\sq_figure$example.v:134$14_ADDR Removing $dff cell `$procdff$1065' from module `\top'. Cell `$procdff$1068' is identical to cell `$procdff$1032'. Redirecting output \Q: $memwr$\sq_figure$example.v:307$27_ADDR = $memwr$\sq_figure$example.v:135$15_ADDR Removing $dff cell `$procdff$1068' from module `\top'. Cell `$procdff$1071' is identical to cell `$procdff$1035'. Redirecting output \Q: $memwr$\sq_figure$example.v:308$28_ADDR = $memwr$\sq_figure$example.v:136$16_ADDR Removing $dff cell `$procdff$1071' from module `\top'. Cell `$procdff$1074' is identical to cell `$procdff$1038'. Redirecting output \Q: $memwr$\sq_figure$example.v:309$29_ADDR = $memwr$\sq_figure$example.v:137$17_ADDR Removing $dff cell `$procdff$1074' from module `\top'. Removed a total of 4 cells. 2.7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$229 Root of a mux tree: $procmux$247 (pure) Root of a mux tree: $procmux$262 Root of a mux tree: $procmux$280 (pure) Root of a mux tree: $procmux$289 Root of a mux tree: $procmux$307 (pure) Root of a mux tree: $procmux$313 Root of a mux tree: $procmux$331 (pure) Root of a mux tree: $procmux$337 Root of a mux tree: $procmux$355 (pure) Root of a mux tree: $procmux$361 Root of a mux tree: $procmux$379 (pure) Root of a mux tree: $procmux$385 Root of a mux tree: $procmux$403 (pure) Root of a mux tree: $procmux$409 Root of a mux tree: $procmux$427 (pure) Root of a mux tree: $procmux$439 (pure) Root of a mux tree: $procmux$619 (pure) Root of a mux tree: $procmux$659 Root of a mux tree: $procmux$667 Root of a mux tree: $procmux$680 Root of a mux tree: $procmux$695 (pure) Root of a mux tree: $procmux$702 Root of a mux tree: $procmux$710 Root of a mux tree: $procmux$717 Root of a mux tree: $procmux$728 Root of a mux tree: $procmux$738 (pure) Removing pure flag from root mux $procmux$702. Root of a mux tree: $procmux$745 Root of a mux tree: $procmux$753 Root of a mux tree: $procmux$766 Root of a mux tree: $procmux$781 (pure) Root of a mux tree: $procmux$788 Root of a mux tree: $procmux$796 Root of a mux tree: $procmux$803 Root of a mux tree: $procmux$814 Root of a mux tree: $procmux$824 (pure) Removing pure flag from root mux $procmux$788. Root of a mux tree: $procmux$827 (pure) Root of a mux tree: $procmux$839 (pure) Root of a mux tree: $procmux$854 (pure) Root of a mux tree: $procmux$857 Root of a mux tree: $procmux$864 Root of a mux tree: $procmux$872 (pure) Root of a mux tree: $procmux$875 Root of a mux tree: $procmux$882 Root of a mux tree: $procmux$890 (pure) Root of a mux tree: $procmux$896 (pure) Root of a mux tree: $procmux$905 (pure) Root of a mux tree: $procmux$911 (pure) Root of a mux tree: $procmux$917 (pure) Root of a mux tree: $procmux$923 (pure) Root of a mux tree: $procmux$926 (pure) Root of a mux tree: $procmux$929 (pure) Root of a mux tree: $procmux$935 (pure) Root of a mux tree: $procmux$941 (pure) Root of a mux tree: $procmux$948 Root of a mux tree: $procmux$953 (pure) Root of a mux tree: $procmux$973 (pure) Root of a mux tree: $procmux$788 (rerun as non-pure) Root of a mux tree: $procmux$702 (rerun as non-pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1102: { $auto$alumacc.cc:490:replace_alu$1100 [0] $auto$alumacc.cc:490:replace_alu$1100 [1] $auto$alumacc.cc:490:replace_alu$1100 [2] $auto$alumacc.cc:490:replace_alu$1100 [3] $auto$alumacc.cc:490:replace_alu$1100 [4] $auto$alumacc.cc:490:replace_alu$1100 [5] $auto$alumacc.cc:490:replace_alu$1100 [6] $auto$alumacc.cc:490:replace_alu$1100 [7] $auto$alumacc.cc:490:replace_alu$1100 [8] $auto$alumacc.cc:490:replace_alu$1100 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1113: { $auto$alumacc.cc:490:replace_alu$1111 [0] $auto$alumacc.cc:490:replace_alu$1111 [1] $auto$alumacc.cc:490:replace_alu$1111 [2] $auto$alumacc.cc:490:replace_alu$1111 [3] $auto$alumacc.cc:490:replace_alu$1111 [4] $auto$alumacc.cc:490:replace_alu$1111 [5] $auto$alumacc.cc:490:replace_alu$1111 [6] $auto$alumacc.cc:490:replace_alu$1111 [7] $auto$alumacc.cc:490:replace_alu$1111 [8] $auto$alumacc.cc:490:replace_alu$1111 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1129: { $auto$alumacc.cc:490:replace_alu$1127 [0] $auto$alumacc.cc:490:replace_alu$1127 [1] $auto$alumacc.cc:490:replace_alu$1127 [2] $auto$alumacc.cc:490:replace_alu$1127 [3] $auto$alumacc.cc:490:replace_alu$1127 [4] $auto$alumacc.cc:490:replace_alu$1127 [5] $auto$alumacc.cc:490:replace_alu$1127 [6] $auto$alumacc.cc:490:replace_alu$1127 [7] $auto$alumacc.cc:490:replace_alu$1127 [8] $auto$alumacc.cc:490:replace_alu$1127 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1140: { $auto$alumacc.cc:490:replace_alu$1138 [0] $auto$alumacc.cc:490:replace_alu$1138 [1] $auto$alumacc.cc:490:replace_alu$1138 [2] $auto$alumacc.cc:490:replace_alu$1138 [3] $auto$alumacc.cc:490:replace_alu$1138 [4] $auto$alumacc.cc:490:replace_alu$1138 [5] $auto$alumacc.cc:490:replace_alu$1138 [6] $auto$alumacc.cc:490:replace_alu$1138 [7] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1156: { $auto$alumacc.cc:490:replace_alu$1154 [0] $auto$alumacc.cc:490:replace_alu$1154 [1] $auto$alumacc.cc:490:replace_alu$1154 [2] $auto$alumacc.cc:490:replace_alu$1154 [3] $auto$alumacc.cc:490:replace_alu$1154 [4] $auto$alumacc.cc:490:replace_alu$1154 [5] $auto$alumacc.cc:490:replace_alu$1154 [6] $auto$alumacc.cc:490:replace_alu$1154 [7] $auto$alumacc.cc:490:replace_alu$1154 [8] $auto$alumacc.cc:490:replace_alu$1154 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1177: { $auto$alumacc.cc:490:replace_alu$1175 [0] $auto$alumacc.cc:490:replace_alu$1175 [1] $auto$alumacc.cc:490:replace_alu$1175 [2] $auto$alumacc.cc:490:replace_alu$1175 [3] $auto$alumacc.cc:490:replace_alu$1175 [4] $auto$alumacc.cc:490:replace_alu$1175 [5] $auto$alumacc.cc:490:replace_alu$1175 [6] $auto$alumacc.cc:490:replace_alu$1175 [7] $auto$alumacc.cc:490:replace_alu$1175 [8] $auto$alumacc.cc:490:replace_alu$1175 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1193: { $auto$alumacc.cc:490:replace_alu$1191 [0] $auto$alumacc.cc:490:replace_alu$1191 [1] $auto$alumacc.cc:490:replace_alu$1191 [2] $auto$alumacc.cc:490:replace_alu$1191 [3] $auto$alumacc.cc:490:replace_alu$1191 [4] $auto$alumacc.cc:490:replace_alu$1191 [5] $auto$alumacc.cc:490:replace_alu$1191 [6] $auto$alumacc.cc:490:replace_alu$1191 [7] $auto$alumacc.cc:490:replace_alu$1191 [8] $auto$alumacc.cc:490:replace_alu$1191 [9] } New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$1214: { $auto$alumacc.cc:490:replace_alu$1212 [0] $auto$alumacc.cc:490:replace_alu$1212 [1] $auto$alumacc.cc:490:replace_alu$1212 [2] $auto$alumacc.cc:490:replace_alu$1212 [3] $auto$alumacc.cc:490:replace_alu$1212 [4] $auto$alumacc.cc:490:replace_alu$1212 [5] $auto$alumacc.cc:490:replace_alu$1212 [6] $auto$alumacc.cc:490:replace_alu$1212 [7] $auto$alumacc.cc:490:replace_alu$1212 [8] $auto$alumacc.cc:490:replace_alu$1212 [9] } Optimizing cells in module \top. Performed a total of 8 changes. 2.7.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.6. Executing OPT_RMDFF pass (remove dff with constant values). Removing $procdff$1005 ($dff) from module top. Removing $procdff$1006 ($dff) from module top. Removing $procdff$1008 ($dff) from module top. Removing $procdff$1009 ($dff) from module top. Removing $procdff$1011 ($dff) from module top. Removing $procdff$1012 ($dff) from module top. Removing $procdff$1014 ($dff) from module top. Removing $procdff$1015 ($dff) from module top. Removing $procdff$1017 ($dff) from module top. Removing $procdff$1018 ($dff) from module top. Removing $procdff$1020 ($dff) from module top. Removing $procdff$1023 ($dff) from module top. Removing $procdff$1024 ($dff) from module top. Removing $procdff$1026 ($dff) from module top. Removing $procdff$1029 ($dff) from module top. Removing $procdff$1030 ($dff) from module top. Removing $procdff$1032 ($dff) from module top. Removing $procdff$1035 ($dff) from module top. Removing $procdff$1038 ($dff) from module top. Removing $procdff$1041 ($dff) from module top. Removing $procdff$1044 ($dff) from module top. Removing $procdff$1047 ($dff) from module top. Removing $procdff$1050 ($dff) from module top. Removing $procdff$1053 ($dff) from module top. Removing $procdff$1056 ($dff) from module top. Removing $procdff$1059 ($dff) from module top. Removing $procdff$1062 ($dff) from module top. Replaced 27 DFF cells. 2.7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$not' cell `$auto$alumacc.cc:78:get_cf$1151'. removing unused `$not' cell `$auto$alumacc.cc:58:get_gt$1162'. removing unused `$not' cell `$auto$alumacc.cc:58:get_gt$1146'. removing unused `$not' cell `$auto$alumacc.cc:78:get_cf$1257'. removing unused `$not' cell `$auto$alumacc.cc:78:get_cf$1249'. removing unused `$not' cell `$auto$alumacc.cc:58:get_gt$1220'. removing unused `$not' cell `$auto$alumacc.cc:78:get_cf$1209'. removed 101 unused temporary wires. Removed 28 unused cells and 570 unused wires. 2.7.9.8. Executing OPT_EXPR pass (perform const folding). 2.7.9.9. Rerunning OPT passes. (Maybe there is more to do..) 2.7.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$229 Root of a mux tree: $procmux$247 (pure) Root of a mux tree: $procmux$262 Root of a mux tree: $procmux$280 (pure) Root of a mux tree: $procmux$289 Root of a mux tree: $procmux$307 (pure) Root of a mux tree: $procmux$313 Root of a mux tree: $procmux$331 (pure) Root of a mux tree: $procmux$337 Root of a mux tree: $procmux$355 (pure) Root of a mux tree: $procmux$361 Root of a mux tree: $procmux$379 (pure) Root of a mux tree: $procmux$385 Root of a mux tree: $procmux$403 (pure) Root of a mux tree: $procmux$409 Root of a mux tree: $procmux$427 (pure) Root of a mux tree: $procmux$439 (pure) Root of a mux tree: $procmux$619 (pure) Root of a mux tree: $procmux$659 Root of a mux tree: $procmux$667 Root of a mux tree: $procmux$680 Root of a mux tree: $procmux$695 (pure) Root of a mux tree: $procmux$702 Root of a mux tree: $procmux$710 Root of a mux tree: $procmux$717 Root of a mux tree: $procmux$728 Root of a mux tree: $procmux$738 (pure) Removing pure flag from root mux $procmux$702. Root of a mux tree: $procmux$745 Root of a mux tree: $procmux$753 Root of a mux tree: $procmux$766 Root of a mux tree: $procmux$781 (pure) Root of a mux tree: $procmux$788 Root of a mux tree: $procmux$796 Root of a mux tree: $procmux$803 Root of a mux tree: $procmux$814 Root of a mux tree: $procmux$824 (pure) Removing pure flag from root mux $procmux$788. Root of a mux tree: $procmux$827 (pure) Root of a mux tree: $procmux$839 (pure) Root of a mux tree: $procmux$854 (pure) Root of a mux tree: $procmux$857 Root of a mux tree: $procmux$864 Root of a mux tree: $procmux$872 (pure) Root of a mux tree: $procmux$875 Root of a mux tree: $procmux$882 Root of a mux tree: $procmux$890 (pure) Root of a mux tree: $procmux$896 (pure) Root of a mux tree: $procmux$905 (pure) Root of a mux tree: $procmux$911 (pure) Root of a mux tree: $procmux$917 (pure) Root of a mux tree: $procmux$923 (pure) Root of a mux tree: $procmux$926 (pure) Root of a mux tree: $procmux$929 (pure) Root of a mux tree: $procmux$935 (pure) Root of a mux tree: $procmux$941 (pure) Root of a mux tree: $procmux$948 Root of a mux tree: $procmux$953 (pure) Root of a mux tree: $procmux$973 (pure) Root of a mux tree: $procmux$788 (rerun as non-pure) Root of a mux tree: $procmux$702 (rerun as non-pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.7.9.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 28 unused cells and 570 unused wires. 2.7.9.15. Executing OPT_EXPR pass (perform const folding). 2.7.9.16. Finished OPT passes. (There is nothing left to do.) 2.7.10. Executing FSM pass (extract and optimize FSM). 2.7.10.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.$memwr$\sq_figure$example.v:126$6_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$memwr$\sq_figure$example.v:306$26_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.vga_b_r as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. Not marking top.vga_r_r as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. 2.7.10.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.7.10.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.7.10.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 28 unused cells and 570 unused wires. 2.7.10.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.7.10.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.7.10.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.7.10.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.7.11. Executing OPT pass (performing simple optimizations). 2.7.11.1. Executing OPT_EXPR pass (perform const folding). 2.7.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.11.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 28 unused cells and 570 unused wires. 2.7.11.5. Finished fast OPT passes. 2.7.12. Executing MEMORY pass. 2.7.12.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$memwr$\sq_figure$example.v:126$195' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:127$196' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:128$197' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:129$198' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:130$199' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:131$200' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:132$201' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:133$202' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:134$203' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:135$204' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:136$205' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:137$206' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:138$207' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:139$208' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:140$209' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:141$210' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:142$211' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:143$212' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:144$213' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:145$214' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:306$215' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:307$216' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:308$217' in module `\top': merged $dff to cell. Checking cell `$memwr$\sq_figure$example.v:309$218' in module `\top': merged $dff to cell. Checking cell `$memrd$\sq_figure$example.v:202$155' in module `\top': no (compatible) $dff found. Checking cell `$memrd$\sq_figure$example.v:306$178' in module `\top': no (compatible) $dff found. Checking cell `$memrd$\sq_figure$example.v:307$180' in module `\top': no (compatible) $dff found. Checking cell `$memrd$\sq_figure$example.v:308$182' in module `\top': no (compatible) $dff found. Checking cell `$memrd$\sq_figure$example.v:309$184' in module `\top': no (compatible) $dff found. 2.7.12.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$dff' cell `$procdff$1007'. removing unused `$dff' cell `$procdff$1066'. removing unused `$dff' cell `$procdff$1067'. removing unused `$dff' cell `$procdff$1069'. removing unused `$dff' cell `$procdff$1072'. removing unused `$dff' cell `$procdff$1075'. removed 6 unused temporary wires. Removed 34 unused cells and 576 unused wires. 2.7.12.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.sq_figure by address: New clock domain: posedge \clk_div [1] Port 0 ($memwr$\sq_figure$example.v:126$195) has addr 5'00000. Active bits: 11111111111111111111 Port 1 ($memwr$\sq_figure$example.v:127$196) has addr 5'00001. Active bits: 11111111111111111111 Port 2 ($memwr$\sq_figure$example.v:128$197) has addr 5'00010. Active bits: 11111111111111111111 Port 3 ($memwr$\sq_figure$example.v:129$198) has addr 5'00011. Active bits: 11111111111111111111 Port 4 ($memwr$\sq_figure$example.v:130$199) has addr 5'00100. Active bits: 11111111111111111111 Port 5 ($memwr$\sq_figure$example.v:131$200) has addr 5'00101. Active bits: 11111111111111111111 Port 6 ($memwr$\sq_figure$example.v:132$201) has addr 5'00110. Active bits: 11111111111111111111 Port 7 ($memwr$\sq_figure$example.v:133$202) has addr 5'00111. Active bits: 11111111111111111111 Port 8 ($memwr$\sq_figure$example.v:134$203) has addr 5'01000. Active bits: 11111111111111111111 Port 9 ($memwr$\sq_figure$example.v:135$204) has addr 5'01001. Active bits: 11111111111111111111 Port 10 ($memwr$\sq_figure$example.v:136$205) has addr 5'01010. Active bits: 11111111111111111111 Port 11 ($memwr$\sq_figure$example.v:137$206) has addr 5'01011. Active bits: 11111111111111111111 Port 12 ($memwr$\sq_figure$example.v:138$207) has addr 5'01100. Active bits: 11111111111111111111 Port 13 ($memwr$\sq_figure$example.v:139$208) has addr 5'01101. Active bits: 11111111111111111111 Port 14 ($memwr$\sq_figure$example.v:140$209) has addr 5'01110. Active bits: 11111111111111111111 Port 15 ($memwr$\sq_figure$example.v:141$210) has addr 5'01111. Active bits: 11111111111111111111 Port 16 ($memwr$\sq_figure$example.v:142$211) has addr 5'10000. Active bits: 11111111111111111111 Port 17 ($memwr$\sq_figure$example.v:143$212) has addr 5'10001. Active bits: 11111111111111111111 Port 18 ($memwr$\sq_figure$example.v:144$213) has addr 5'10010. Active bits: 11111111111111111111 Port 19 ($memwr$\sq_figure$example.v:145$214) has addr 5'10011. Active bits: 11111111111111111111 Port 20 ($memwr$\sq_figure$example.v:306$215) has addr 5'01000. Active bits: 11111111111111111111 Merging port 8 into this one. Creating collosion-detect logic for port 9. Creating collosion-detect logic for port 10. Creating collosion-detect logic for port 11. Creating collosion-detect logic for port 12. Creating collosion-detect logic for port 13. Creating collosion-detect logic for port 14. Creating collosion-detect logic for port 15. Creating collosion-detect logic for port 16. Creating collosion-detect logic for port 17. Creating collosion-detect logic for port 18. Creating collosion-detect logic for port 19. Creating logic for merging DATA and EN ports. Active bits: 11111111111111111111 Port 21 ($memwr$\sq_figure$example.v:307$216) has addr 5'01001. Active bits: 11111111111111111111 Merging port 9 into this one. Creating collosion-detect logic for port 10. Creating collosion-detect logic for port 11. Creating collosion-detect logic for port 12. Creating collosion-detect logic for port 13. Creating collosion-detect logic for port 14. Creating collosion-detect logic for port 15. Creating collosion-detect logic for port 16. Creating collosion-detect logic for port 17. Creating collosion-detect logic for port 18. Creating collosion-detect logic for port 19. Creating collosion-detect logic for port 20. Creating logic for merging DATA and EN ports. Active bits: 11111111111111111111 Port 22 ($memwr$\sq_figure$example.v:308$217) has addr 5'01010. Active bits: 11111111111111111111 Merging port 10 into this one. Creating collosion-detect logic for port 11. Creating collosion-detect logic for port 12. Creating collosion-detect logic for port 13. Creating collosion-detect logic for port 14. Creating collosion-detect logic for port 15. Creating collosion-detect logic for port 16. Creating collosion-detect logic for port 17. Creating collosion-detect logic for port 18. Creating collosion-detect logic for port 19. Creating collosion-detect logic for port 20. Creating collosion-detect logic for port 21. Creating logic for merging DATA and EN ports. Active bits: 11111111111111111111 Port 23 ($memwr$\sq_figure$example.v:309$218) has addr 5'01011. Active bits: 11111111111111111111 Merging port 11 into this one. Creating collosion-detect logic for port 12. Creating collosion-detect logic for port 13. Creating collosion-detect logic for port 14. Creating collosion-detect logic for port 15. Creating collosion-detect logic for port 16. Creating collosion-detect logic for port 17. Creating collosion-detect logic for port 18. Creating collosion-detect logic for port 19. Creating collosion-detect logic for port 20. Creating collosion-detect logic for port 21. Creating collosion-detect logic for port 22. Creating logic for merging DATA and EN ports. Active bits: 11111111111111111111 Consolidating write ports of memory top.sq_figure using sat-based resource sharing: Port 0 ($memwr$\sq_figure$example.v:126$195) on posedge \clk_div [1]: considered Port 1 ($memwr$\sq_figure$example.v:127$196) on posedge \clk_div [1]: considered Port 2 ($memwr$\sq_figure$example.v:128$197) on posedge \clk_div [1]: considered Port 3 ($memwr$\sq_figure$example.v:129$198) on posedge \clk_div [1]: considered Port 4 ($memwr$\sq_figure$example.v:130$199) on posedge \clk_div [1]: considered Port 5 ($memwr$\sq_figure$example.v:131$200) on posedge \clk_div [1]: considered Port 6 ($memwr$\sq_figure$example.v:132$201) on posedge \clk_div [1]: considered Port 7 ($memwr$\sq_figure$example.v:133$202) on posedge \clk_div [1]: considered Port 8 ($memwr$\sq_figure$example.v:138$207) on posedge \clk_div [1]: considered Port 9 ($memwr$\sq_figure$example.v:139$208) on posedge \clk_div [1]: considered Port 10 ($memwr$\sq_figure$example.v:140$209) on posedge \clk_div [1]: considered Port 11 ($memwr$\sq_figure$example.v:141$210) on posedge \clk_div [1]: considered Port 12 ($memwr$\sq_figure$example.v:142$211) on posedge \clk_div [1]: considered Port 13 ($memwr$\sq_figure$example.v:143$212) on posedge \clk_div [1]: considered Port 14 ($memwr$\sq_figure$example.v:144$213) on posedge \clk_div [1]: considered Port 15 ($memwr$\sq_figure$example.v:145$214) on posedge \clk_div [1]: considered Port 16 ($memwr$\sq_figure$example.v:306$215) on posedge \clk_div [1]: considered Port 17 ($memwr$\sq_figure$example.v:307$216) on posedge \clk_div [1]: considered Port 18 ($memwr$\sq_figure$example.v:308$217) on posedge \clk_div [1]: considered Port 19 ($memwr$\sq_figure$example.v:309$218) on posedge \clk_div [1]: considered Common input cone for all EN signals: 183 cells. Size of unconstrained SAT problem: 897 variables, 2274 clauses According to SAT solver sharing of port 0 with port 1 is not possible. According to SAT solver sharing of port 1 with port 2 is not possible. According to SAT solver sharing of port 2 with port 3 is not possible. According to SAT solver sharing of port 3 with port 4 is not possible. According to SAT solver sharing of port 4 with port 5 is not possible. According to SAT solver sharing of port 5 with port 6 is not possible. According to SAT solver sharing of port 6 with port 7 is not possible. According to SAT solver sharing of port 7 with port 8 is not possible. According to SAT solver sharing of port 8 with port 9 is not possible. According to SAT solver sharing of port 9 with port 10 is not possible. According to SAT solver sharing of port 10 with port 11 is not possible. According to SAT solver sharing of port 11 with port 12 is not possible. According to SAT solver sharing of port 12 with port 13 is not possible. According to SAT solver sharing of port 13 with port 14 is not possible. According to SAT solver sharing of port 14 with port 15 is not possible. According to SAT solver sharing of port 15 with port 16 is not possible. According to SAT solver sharing of port 16 with port 17 is not possible. According to SAT solver sharing of port 17 with port 18 is not possible. According to SAT solver sharing of port 18 with port 19 is not possible. 2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 34 unused cells and 576 unused wires. 2.7.12.5. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\sq_figure' in module `\top': $memwr$\sq_figure$example.v:126$195 ($memwr) $memwr$\sq_figure$example.v:127$196 ($memwr) $memwr$\sq_figure$example.v:128$197 ($memwr) $memwr$\sq_figure$example.v:129$198 ($memwr) $memwr$\sq_figure$example.v:130$199 ($memwr) $memwr$\sq_figure$example.v:131$200 ($memwr) $memwr$\sq_figure$example.v:132$201 ($memwr) $memwr$\sq_figure$example.v:133$202 ($memwr) $memwr$\sq_figure$example.v:138$207 ($memwr) $memwr$\sq_figure$example.v:139$208 ($memwr) $memwr$\sq_figure$example.v:140$209 ($memwr) $memwr$\sq_figure$example.v:141$210 ($memwr) $memwr$\sq_figure$example.v:142$211 ($memwr) $memwr$\sq_figure$example.v:143$212 ($memwr) $memwr$\sq_figure$example.v:144$213 ($memwr) $memwr$\sq_figure$example.v:145$214 ($memwr) $memwr$\sq_figure$example.v:306$215 ($memwr) $memwr$\sq_figure$example.v:307$216 ($memwr) $memwr$\sq_figure$example.v:308$217 ($memwr) $memwr$\sq_figure$example.v:309$218 ($memwr) $memrd$\sq_figure$example.v:202$155 ($memrd) $memrd$\sq_figure$example.v:306$178 ($memrd) $memrd$\sq_figure$example.v:307$180 ($memrd) $memrd$\sq_figure$example.v:308$182 ($memrd) $memrd$\sq_figure$example.v:309$184 ($memrd) 2.7.13. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 34 unused cells and 576 unused wires. 2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.sq_figure: Properties: ports=25 bits=400 rports=5 wports=20 dbits=20 abits=5 words=20 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=236 dwaste=12 bwaste=4016 waste=4016 efficiency=4 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \clk_div [1]. Mapped to bram port B1. Write port #1 is in clock domain \clk_div [1]. Failed to map write port #1. Mapping to bram type $__ICE40_RAM4K_M0 failed. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=492 dwaste=4 bwaste=4016 waste=4016 efficiency=3 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \clk_div [1]. Mapped to bram port B1. Write port #1 is in clock domain \clk_div [1]. Failed to map write port #1. Mapping to bram type $__ICE40_RAM4K_M123 failed. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1004 dwaste=0 bwaste=4016 waste=4016 efficiency=1 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'min efficiency 2' not met. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=2028 dwaste=0 bwaste=4056 waste=4056 efficiency=0 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'min efficiency 2' not met. No acceptable bram resources found. 2.9. Executing TECHMAP pass (map to technology primitives). 2.9.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. No more expansions possible. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1361' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1360 = 1'0'. Replacing $mux cell `$procmux$439' (mux_sel01) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:126$6_EN[19:0]$47 [19] = \reset'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1364' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1365 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1329' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1328 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1332' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1333 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1321' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1320 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1324' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1325 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1313' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1312 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1316' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1317 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1305' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1304 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1308' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1309 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1297' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1296 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1300' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1301 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1281' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1280 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1284' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1285 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1286' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1287 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1289' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1288 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1292' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1293 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1294' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1295 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1302' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1303 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1310' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1311 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1318' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1319 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1326' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1327 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1334' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1335 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1337' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1336 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1340' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1341 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1342' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1343 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1345' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1344 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1348' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1349 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1350' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1351 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1353' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1352 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1356' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1357 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1358' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1359 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1366' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1367 = \reset'. Replacing $and cell `$auto$memory_share.cc:336:merge_en_data$1370' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1741': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1743': A=1'0, B=1'0 Replacing $or cell `$auto$memory_share.cc:342:merge_en_data$1382' in module `\top' with identity for port B. Replacing $not cell `$auto$memory_share.cc:337:merge_en_data$1372' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1745': A=2'10 Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1427' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1426 = 1'0'. Replacing $mux cell `$procmux$619' (mux_sel01) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_EN[19:0]$107 [19] = $eq$example.v:304$173_Y'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1395' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1394 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1398' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1399 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1400' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1401 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1403' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1402 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1406' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1407 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1408' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1409 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1411' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1410 = 1'0'. Replacing $not cell `$auto$memory_share.cc:337:merge_en_data$1486' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1747': A=2'10 Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1475' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1474 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1478' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1479 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1467' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1466 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1470' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1471 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1459' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1458 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1462' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1463 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1451' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1450 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1454' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1455 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1443' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1442 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1446' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1447 = 1'1'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1414' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1415 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1416' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1417 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1419' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1418 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1422' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1423 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1424' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1425 = \reset'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1430' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1431 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1432' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1433 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1435' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1434 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1438' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1439 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1440' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1441 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1448' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1449 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1456' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1457 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1464' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1465 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1472' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1473 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1480' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1481 = \reset'. Replacing $and cell `$auto$memory_share.cc:336:merge_en_data$1484' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1749': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1751': A=1'0, B=1'0 Replacing $or cell `$auto$memory_share.cc:342:merge_en_data$1496' in module `\top' with identity for port B. Replacing $not cell `$auto$memory_share.cc:337:merge_en_data$1714' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1753': A=2'10 Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1589' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1588 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1592' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1593 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1581' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1580 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1584' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1585 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1573' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1572 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1576' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1577 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1565' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1564 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1568' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1569 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1557' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1556 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1560' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1561 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1549' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1548 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1552' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1553 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1541' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1540 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1544' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1545 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1533' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1532 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1536' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1537 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1525' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1524 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1528' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1529 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1517' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1516 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1520' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1521 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1509' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1508 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1512' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1513 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1514' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1515 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1522' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1523 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1530' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1531 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1538' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1539 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1546' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1547 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1554' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1555 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1562' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1563 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1570' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1571 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1578' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1579 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1586' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1587 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1594' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1595 = \reset'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1703' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1702 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1706' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1707 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1695' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1694 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1698' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1699 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1687' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1686 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1690' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1691 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1679' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1678 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1682' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1683 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1671' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1670 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1674' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1675 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1663' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1662 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1666' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1667 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1655' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1654 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1658' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1659 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1647' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1646 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1650' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1651 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1639' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1638 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1642' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1643 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1631' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1630 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1634' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1635 = 1'1'. Replacing $eq cell `$auto$memory_share.cc:434:consolidate_wr_by_addr$1623' (isneq) in module `\top' with constant driver `$auto$memory_share.cc:433:consolidate_wr_by_addr$1622 = 1'0'. Replacing $mux cell `$auto$memory_share.cc:268:mask_en_naive$1626' (0) in module `\top' with constant driver `$auto$rtlil.cc:1741:Mux$1627 = 1'1'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1628' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1629 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1636' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1637 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1644' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1645 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1652' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1653 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1660' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1661 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1668' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1669 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1676' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1677 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1684' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1685 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1692' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1693 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1700' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1701 = \reset'. Replacing $and cell `$auto$memory_share.cc:269:mask_en_naive$1708' (and_or_buffer) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$1709 = \reset'. Replacing $and cell `$auto$memory_share.cc:336:merge_en_data$1712' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1755': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1757': A=1'0, B=1'0 Replacing $or cell `$auto$memory_share.cc:342:merge_en_data$1724' in module `\top' with identity for port B. Replacing $not cell `$auto$memory_share.cc:337:merge_en_data$1600' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1759': A=2'10 Replacing $and cell `$auto$memory_share.cc:336:merge_en_data$1598' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1761': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1763': A=1'0, B=1'0 Replacing $or cell `$auto$memory_share.cc:342:merge_en_data$1610' in module `\top' with identity for port B. Replacing $mux cell `$procmux$896' (mux_sel01) in module `\top' with constant driver `$0\disp_en[0:0] = $logic_and$example.v:186$134_Y'. Replacing $mux cell `$procmux$926' (mux_sel01) in module `\top' with constant driver `$0\reset[0:0] = $auto$rtlil.cc:1698:Or$1145'. Replacing $mux cell `$procmux$941' (mux_sel01) in module `\top' with constant driver `$0\vga_hs_r[0:0] = $logic_or$example.v:168$126_Y'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1743' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1742 = 1'0'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1741' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1740 = \reset'. Replacing $pos cell `$auto$memory_share.cc:342:merge_en_data$1382' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1765': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1767': A=1'0 Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1745' (2'10) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1744 = 2'01'. Replacing $and cell `$auto$memory_share.cc:337:merge_en_data$1374' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1769': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1771': A=1'0, B=1'0 Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1747' (2'10) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1746 = 2'01'. Replacing $and cell `$auto$memory_share.cc:337:merge_en_data$1488' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1773': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1775': A=1'0, B=1'0 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1749' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1748 = \reset'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1751' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1750 = 1'0'. Replacing $pos cell `$auto$memory_share.cc:342:merge_en_data$1496' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1777': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1779': A=1'0 Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1753' (2'10) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1752 = 2'01'. Replacing $and cell `$auto$memory_share.cc:337:merge_en_data$1716' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1781': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1783': A=1'0, B=1'0 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1755' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1754 = \reset'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1757' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1756 = 1'0'. Replacing $pos cell `$auto$memory_share.cc:342:merge_en_data$1724' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1785': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1787': A=1'0 Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1759' (2'10) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1758 = 2'01'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1761' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1760 = \reset'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1763' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1762 = 1'0'. Replacing $and cell `$auto$memory_share.cc:337:merge_en_data$1602' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1789': A=1'1, B=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1791': A=1'0, B=1'0 Replacing $pos cell `$auto$memory_share.cc:342:merge_en_data$1610' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1793': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1795': A=1'0 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1771' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1770 = 1'0'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1769' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1768 = \reset'. Replacing $not cell `$auto$memory_share.cc:343:merge_en_data$1384' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1797': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1799': A=1'0 Replacing $pos cell `$auto$opt_expr.cc:158:group_cell_inputs$1767' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1766 = 1'0'. Replacing $and cell `$auto$memory_share.cc:343:merge_en_data$1386' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1801': A={ $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 $auto$opt_expr.cc:145:group_cell_inputs$1764 }, B=$auto$rtlil.cc:1667:Not$1385 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1803': A=1'0, B=1'0 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1775' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1774 = 1'0'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1773' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1772 = \reset'. Replacing $not cell `$auto$memory_share.cc:343:merge_en_data$1498' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1805': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1807': A=1'0 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1783' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1782 = 1'0'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1781' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1780 = \reset'. Replacing $not cell `$auto$memory_share.cc:343:merge_en_data$1726' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1809': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1811': A=1'0 Replacing $pos cell `$auto$opt_expr.cc:158:group_cell_inputs$1787' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1786 = 1'0'. Replacing $and cell `$auto$memory_share.cc:343:merge_en_data$1728' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1813': A={ $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 $auto$opt_expr.cc:145:group_cell_inputs$1784 }, B=$auto$rtlil.cc:1667:Not$1727 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1815': A=1'0, B=1'0 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1789' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1788 = \reset'. Replacing $pos cell `$auto$opt_expr.cc:158:group_cell_inputs$1779' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1778 = 1'0'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1791' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1790 = 1'0'. Replacing $not cell `$auto$memory_share.cc:343:merge_en_data$1612' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1817': A=\reset New cell `$auto$opt_expr.cc:158:group_cell_inputs$1819': A=1'0 Replacing $pos cell `$auto$opt_expr.cc:158:group_cell_inputs$1795' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1794 = 1'0'. Replacing $and cell `$auto$memory_share.cc:343:merge_en_data$1614' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1821': A={ $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 $auto$opt_expr.cc:145:group_cell_inputs$1792 }, B=$auto$rtlil.cc:1667:Not$1613 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1823': A=1'0, B=1'0 Replacing $and cell `$auto$memory_share.cc:343:merge_en_data$1500' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1825': A={ $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 $auto$opt_expr.cc:145:group_cell_inputs$1776 }, B=$auto$rtlil.cc:1667:Not$1499 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1827': A=1'0, B=1'0 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1803' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1802 = 1'0'. Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1799' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1798 = 1'1'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1801' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1829': A=1'1, B=$auto$opt_expr.cc:145:group_cell_inputs$1764 Replacing $or cell `$auto$memory_share.cc:345:merge_en_data$1388' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1831': A=$auto$opt_expr.cc:145:group_cell_inputs$1800, B=$auto$rtlil.cc:1697:And$1377 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1833': A=1'0, B=$auto$rtlil.cc:1697:And$1377 [0] Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1807' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1806 = 1'1'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1825' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1835': A=1'1, B=$auto$opt_expr.cc:145:group_cell_inputs$1776 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1815' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1814 = 1'0'. Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1811' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1810 = 1'1'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1813' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1837': A=1'1, B=$auto$opt_expr.cc:145:group_cell_inputs$1784 Replacing $or cell `$auto$memory_share.cc:345:merge_en_data$1730' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1839': A=$auto$opt_expr.cc:145:group_cell_inputs$1812, B=$auto$rtlil.cc:1697:And$1719 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1841': A=1'0, B=$auto$rtlil.cc:1697:And$1719 [0] Replacing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1819' (1'0) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1818 = 1'1'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1821' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1843': A=1'1, B=$auto$opt_expr.cc:145:group_cell_inputs$1792 Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1823' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1822 = 1'0'. Replacing $or cell `$auto$memory_share.cc:345:merge_en_data$1616' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1845': A=$auto$opt_expr.cc:145:group_cell_inputs$1820, B=$auto$rtlil.cc:1697:And$1605 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1847': A=1'0, B=$auto$rtlil.cc:1697:And$1605 [0] Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1827' (const_and) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1826 = 1'0'. Replacing $or cell `$auto$memory_share.cc:345:merge_en_data$1502' in module `top' with cells using grouped bits: New cell `$auto$opt_expr.cc:158:group_cell_inputs$1849': A=$auto$opt_expr.cc:145:group_cell_inputs$1824, B=$auto$rtlil.cc:1697:And$1491 [19:1] New cell `$auto$opt_expr.cc:158:group_cell_inputs$1851': A=1'0, B=$auto$rtlil.cc:1697:And$1491 [0] Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1829' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1828 = $auto$opt_expr.cc:145:group_cell_inputs$1764'. Replacing $or cell `$auto$opt_expr.cc:158:group_cell_inputs$1833' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1832 = $auto$rtlil.cc:1697:And$1377 [0]'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1843' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1842 = $auto$opt_expr.cc:145:group_cell_inputs$1792'. Replacing $or cell `$auto$opt_expr.cc:158:group_cell_inputs$1851' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1850 = $auto$rtlil.cc:1697:And$1491 [0]'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1835' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1834 = $auto$opt_expr.cc:145:group_cell_inputs$1776'. Replacing $or cell `$auto$opt_expr.cc:158:group_cell_inputs$1841' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1840 = $auto$rtlil.cc:1697:And$1719 [0]'. Replacing $and cell `$auto$opt_expr.cc:158:group_cell_inputs$1837' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1836 = $auto$opt_expr.cc:145:group_cell_inputs$1784'. Replacing $or cell `$auto$opt_expr.cc:158:group_cell_inputs$1847' (and_or_buffer) in module `\top' with constant driver `$auto$opt_expr.cc:145:group_cell_inputs$1846 = $auto$rtlil.cc:1697:And$1605 [0]'. 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1624' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1625 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1624' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1510' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1511 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1510' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1518' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1519 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1518' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1526' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1527 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1526' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1534' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1535 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1534' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1542' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1543 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1542' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1550' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1551 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1550' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1558' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1559 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1558' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1566' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1567 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1566' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1574' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1575 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1574' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1582' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1476'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1583 = $auto$rtlil.cc:1667:Not$1477 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1582' from module `\top'. Cell `$auto$memory_share.cc:325:merge_en_data$1482' is identical to cell `$auto$memory_share.cc:325:merge_en_data$1368'. Redirecting output \Y: $auto$rtlil.cc:1698:Or$1483 = $auto$rtlil.cc:1698:Or$1369 Removing $or cell `$auto$memory_share.cc:325:merge_en_data$1482' from module `\top'. Cell `$auto$memory_share.cc:325:merge_en_data$1596' is identical to cell `$auto$memory_share.cc:325:merge_en_data$1368'. Redirecting output \Y: $auto$rtlil.cc:1698:Or$1597 = $auto$rtlil.cc:1698:Or$1369 Removing $or cell `$auto$memory_share.cc:325:merge_en_data$1596' from module `\top'. Cell `$auto$memory_share.cc:325:merge_en_data$1710' is identical to cell `$auto$memory_share.cc:325:merge_en_data$1368'. Redirecting output \Y: $auto$rtlil.cc:1698:Or$1711 = $auto$rtlil.cc:1698:Or$1369 Removing $or cell `$auto$memory_share.cc:325:merge_en_data$1710' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1468' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1469 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1468' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1436' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1437 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1436' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1362' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1363 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1362' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1420' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1421 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1420' from module `\top'. Cell `$auto$opt_expr.cc:158:group_cell_inputs$1793' is identical to cell `$auto$opt_expr.cc:158:group_cell_inputs$1765'. Redirecting output \Y: $auto$opt_expr.cc:145:group_cell_inputs$1792 = $auto$opt_expr.cc:145:group_cell_inputs$1764 Removing $pos cell `$auto$opt_expr.cc:158:group_cell_inputs$1793' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1672' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1673 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1672' from module `\top'. Cell `$auto$opt_expr.cc:158:group_cell_inputs$1785' is identical to cell `$auto$opt_expr.cc:158:group_cell_inputs$1765'. Redirecting output \Y: $auto$opt_expr.cc:145:group_cell_inputs$1784 = $auto$opt_expr.cc:145:group_cell_inputs$1764 Removing $pos cell `$auto$opt_expr.cc:158:group_cell_inputs$1785' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1298' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1299 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1298' from module `\top'. Cell `$auto$opt_expr.cc:158:group_cell_inputs$1777' is identical to cell `$auto$opt_expr.cc:158:group_cell_inputs$1765'. Redirecting output \Y: $auto$opt_expr.cc:145:group_cell_inputs$1776 = $auto$opt_expr.cc:145:group_cell_inputs$1764 Removing $pos cell `$auto$opt_expr.cc:158:group_cell_inputs$1777' from module `\top'. Cell `$auto$opt_expr.cc:158:group_cell_inputs$1797' is identical to cell `$auto$opt_expr.cc:158:group_cell_inputs$1805'. Redirecting output \Y: $auto$opt_expr.cc:145:group_cell_inputs$1796 = $auto$opt_expr.cc:145:group_cell_inputs$1804 Removing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1797' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1314' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1315 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1314' from module `\top'. Cell `$auto$opt_expr.cc:158:group_cell_inputs$1817' is identical to cell `$auto$opt_expr.cc:158:group_cell_inputs$1805'. Redirecting output \Y: $auto$opt_expr.cc:145:group_cell_inputs$1816 = $auto$opt_expr.cc:145:group_cell_inputs$1804 Removing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1817' from module `\top'. Cell `$auto$opt_expr.cc:158:group_cell_inputs$1809' is identical to cell `$auto$opt_expr.cc:158:group_cell_inputs$1805'. Redirecting output \Y: $auto$opt_expr.cc:145:group_cell_inputs$1808 = $auto$opt_expr.cc:145:group_cell_inputs$1804 Removing $not cell `$auto$opt_expr.cc:158:group_cell_inputs$1809' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1704' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1476'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1705 = $auto$rtlil.cc:1667:Not$1477 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1704' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1282' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1283 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1282' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1656' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1657 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1656' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1688' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1476'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1689 = $auto$rtlil.cc:1667:Not$1477 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1688' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1452' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1453 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1452' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1460' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1461 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1460' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1444' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1445 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1444' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1428' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1429 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1428' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1412' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1413 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1412' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1396' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1397 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1396' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1354' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1355 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1354' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1338' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1339 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1338' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1322' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1323 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1322' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1306' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1307 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1306' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1290' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1291 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1290' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1346' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1347 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1346' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1696' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1476'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1697 = $auto$rtlil.cc:1667:Not$1477 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1696' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1680' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1681 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1680' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1664' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1665 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1664' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1648' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1649 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1648' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1632' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1633 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1632' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1590' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1476'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1591 = $auto$rtlil.cc:1667:Not$1477 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1590' from module `\top'. Cell `$eq$example.v:192$136' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $eq$example.v:192$136_Y = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$eq$example.v:192$136' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1404' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1405 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1404' from module `\top'. Cell `$auto$memory_share.cc:267:mask_en_naive$1330' is identical to cell `$auto$memory_share.cc:267:mask_en_naive$1640'. Redirecting output \Y: $auto$rtlil.cc:1667:Not$1331 = $auto$rtlil.cc:1667:Not$1641 Removing $not cell `$auto$memory_share.cc:267:mask_en_naive$1330' from module `\top'. Removed a total of 52 cells. 2.10.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing buffer cell `$auto$opt_expr.cc:158:group_cell_inputs$1765': $auto$opt_expr.cc:145:group_cell_inputs$1764 = \reset removing unused `$not' cell `$auto$memory_share.cc:267:mask_en_naive$1476'. removing unused `$not' cell `$auto$opt_expr.cc:158:group_cell_inputs$1805'. removed 260 unused temporary wires. Removed 36 unused cells and 836 unused wires. 2.10.5. Finished fast OPT passes. 2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). Mapping memory cell \sq_figure in module \top: created 20 $dff cells and 0 static cells of width 20. read interface: 0 $dff and 155 $mux cells. write interface: 400 write mux blocks. 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][10]$a$1968 [16:4] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$b$2065 [19] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$b$1984 [3:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][13]$a$2070 [16:9] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$b$2065 [17:15] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$b$1984 [5:4] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$b$1984 [7:6] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][13]$b$2071 [19:17] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][13]$a$2070 [8:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [3] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [2] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$a$1983 [18:11] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][10]$a$2061 [19] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$b$1984 [18:8] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$b$2065 [18] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][14]$b$1981 [15:6] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [14] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [6] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [9:8] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [12:11] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][10]$a$1968 [17] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$a$1983 [8:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][14]$b$1981 [3] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [5:4] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$b$1984 [19] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][14]$b$1981 [4] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [10] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][14]$b$1981 [5] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [13] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][10]$a$1968 [19:18] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$a$1983 [19] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][14]$b$1981 [2:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [7] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$a$1983 [10] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [1] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][15]$a$1983 [9] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][14]$a$2259 [19] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][13]$b$2257 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][13]$a$2256 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][12]$b$2254 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][12]$a$2253 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][11]$b$2251 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][11]$a$2250 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][10]$b$2248 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][10]$a$2247 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$a$2064 [19:15] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][10]$b$2062 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][10]$a$2061 [18:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][15]$b$2077 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][15]$a$2076 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][14]$b$2074 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][14]$a$2073 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][13]$b$2071 [16:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][15]$b$2170 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][15]$a$2169 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][14]$b$2167 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][14]$a$2166 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][13]$b$2164 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][13]$a$2163 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][12]$b$2161 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][12]$a$2160 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][11]$b$2158 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][11]$a$2157 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][10]$b$2155 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[2][4][10]$a$2154 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][13]$a$2070 [19:17] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][12]$b$2068 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][12]$a$2067 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[1][4][11]$b$2065 [14:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][15]$b$2263 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][15]$a$2262 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][14]$b$2260 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[3][4][14]$a$2259 [18:0] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][15]$b$2356 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][15]$a$2355 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][14]$b$2353 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][14]$a$2352 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][13]$b$2350 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][13]$a$2349 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][12]$b$2347 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][12]$a$2346 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][11]$b$2344 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][11]$a$2343 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][10]$b$2341 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[4][4][10]$a$2340 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][14]$b$1981 [19:16] Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][14]$a$1980 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][13]$b$1978 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][13]$a$1977 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][12]$b$1975 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][12]$a$1974 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][11]$b$1972 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][11]$a$1971 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][10]$b$1969 Setting undriven signal in top to undef: $memory\sq_figure$rdmux[0][4][10]$a$1968 [3:0] Replacing $eq cell `$auto$memory_map.cc:65:addr_decode$2357' (empty) in module `\top' with constant driver `$auto$rtlil.cc:1709:Eq$2358 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2359' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2360 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2361' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2362 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2363' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2364 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[0][0][0]$2365' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[0][0][0]$y$2366 = \reset'. Replacing $eq cell `$auto$memory_map.cc:65:addr_decode$2369' (isneq) in module `\top' with constant driver `$auto$rtlil.cc:1709:Eq$2370 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2371' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2372 = 1'0'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][5]$2231' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][2]$b$2200 = $memory\sq_figure$rdmux[3][4][5]$a$2232'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][4]$2228' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][2]$a$2199 = $memory\sq_figure$rdmux[3][4][4]$a$2229'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][2]$2198' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][1]$a$2184 = $memory\sq_figure$rdmux[3][3][2]$b$2200'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][15]$2075' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][7]$b$2029 = $memory\sq_figure$rdmux[1][4][15]$a$2076'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][14]$2072' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][7]$a$2028 = $memory\sq_figure$rdmux[1][4][14]$a$2073'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][7]$2027' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][3]$b$2005 = $memory\sq_figure$rdmux[1][3][7]$a$2028'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][12]$2066' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][6]$a$2025 = $memory\sq_figure$rdmux[1][4][12]$a$2067'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][13]$2069' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][6]$b$2026 = $memory\sq_figure$rdmux[1][4][13]$a$2070'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][6]$2024' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][3]$a$2004 = $memory\sq_figure$rdmux[1][3][6]$a$2025'. Replacing $mux cell `$memory\sq_figure$rdmux[1][2][3]$2003' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][1][1]$b$1993 = $memory\sq_figure$rdmux[1][2][3]$a$2004'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][10]$2060' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][5]$a$2022 = $memory\sq_figure$rdmux[1][4][10]$a$2061'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][11]$2063' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][5]$b$2023 = $memory\sq_figure$rdmux[1][4][11]$a$2064'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][5]$2021' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][2]$b$2002 = $memory\sq_figure$rdmux[1][3][5]$a$2022'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][9]$2057' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][4]$b$2020 = $memory\sq_figure$rdmux[1][4][9]$a$2058'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][8]$2054' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][4]$a$2019 = $memory\sq_figure$rdmux[1][4][8]$a$2055'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][4]$2018' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][2]$a$2001 = $memory\sq_figure$rdmux[1][3][4]$a$2019'. Replacing $mux cell `$memory\sq_figure$rdmux[1][2][2]$2000' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][1][1]$a$1992 = $memory\sq_figure$rdmux[1][2][2]$a$2001'. Replacing $mux cell `$memory\sq_figure$rdmux[1][1][1]$1991' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][0][0]$b$1987 = $memory\sq_figure$rdmux[1][1][1]$b$1993'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][2]$2036' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][1]$a$2010 = $memory\sq_figure$rdmux[1][4][2]$a$2037'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][3]$2039' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][1]$b$2011 = $memory\sq_figure$rdmux[1][4][3]$a$2040'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][1]$2009' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][0]$b$1996 = $memory\sq_figure$rdmux[1][3][1]$a$2010'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][1]$2033' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][0]$b$2008 = $memory\sq_figure$rdmux[1][4][1]$a$2034'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][0]$2030' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][0]$a$2007 = $memory\sq_figure$rdmux[1][4][0]$a$2031'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][0]$2006' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][0]$a$1995 = $memory\sq_figure$rdmux[1][3][0]$a$2007'. Replacing $mux cell `$memory\sq_figure$rdmux[1][2][0]$1994' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][1][0]$a$1989 = $memory\sq_figure$rdmux[1][2][0]$a$1995'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][7]$2051' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][3]$b$2017 = $memory\sq_figure$rdmux[1][4][7]$a$2052'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][6]$2048' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][3]$a$2016 = $memory\sq_figure$rdmux[1][4][6]$a$2049'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][3]$2015' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][1]$b$1999 = $memory\sq_figure$rdmux[1][3][3]$a$2016'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][5]$2045' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][2]$b$2014 = $memory\sq_figure$rdmux[1][4][5]$a$2046'. Replacing $mux cell `$memory\sq_figure$rdmux[1][4][4]$2042' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][3][2]$a$2013 = $memory\sq_figure$rdmux[1][4][4]$a$2043'. Replacing $mux cell `$memory\sq_figure$rdmux[1][3][2]$2012' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][2][1]$a$1998 = $memory\sq_figure$rdmux[1][3][2]$a$2013'. Replacing $mux cell `$memory\sq_figure$rdmux[1][2][1]$1997' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][1][0]$b$1990 = $memory\sq_figure$rdmux[1][2][1]$a$1998'. Replacing $mux cell `$memory\sq_figure$rdmux[1][1][0]$1988' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[1][0][0]$a$1986 = $memory\sq_figure$rdmux[1][1][0]$b$1990'. Replacing $mux cell `$memory\sq_figure$rdmux[1][0][0]$1985' (0) in module `\top' with constant driver `$memrd$\sq_figure$example.v:306$178_DATA = $memory\sq_figure$rdmux[1][0][0]$a$1986'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][8]$2147' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][4]$a$2112 = $memory\sq_figure$rdmux[2][4][8]$b$2149'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][9]$2150' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][4]$b$2113 = $memory\sq_figure$rdmux[2][4][9]$b$2152'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][4]$2111' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][2]$a$2094 = $memory\sq_figure$rdmux[2][3][4]$a$2112'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][8]$2240' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][4]$a$2205 = $memory\sq_figure$rdmux[3][4][8]$a$2241'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][9]$2243' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][4]$b$2206 = $memory\sq_figure$rdmux[3][4][9]$a$2244'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][4]$2204' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][2]$a$2187 = $memory\sq_figure$rdmux[3][3][4]$b$2206'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][11]$2249' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][5]$b$2209 = $memory\sq_figure$rdmux[3][4][11]$a$2250'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][10]$2246' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][5]$a$2208 = $memory\sq_figure$rdmux[3][4][10]$a$2247'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][5]$2207' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][2]$b$2188 = $memory\sq_figure$rdmux[3][3][5]$b$2209'. Replacing $mux cell `$memory\sq_figure$rdmux[3][2][2]$2186' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][1][1]$a$2178 = $memory\sq_figure$rdmux[3][2][2]$a$2187'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][14]$2258' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][7]$a$2214 = $memory\sq_figure$rdmux[3][4][14]$a$2259'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][15]$2261' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][7]$b$2215 = $memory\sq_figure$rdmux[3][4][15]$a$2262'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][7]$2213' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][3]$b$2191 = $memory\sq_figure$rdmux[3][3][7]$b$2215'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][12]$2252' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][6]$a$2211 = $memory\sq_figure$rdmux[3][4][12]$a$2253'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][13]$2255' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][6]$b$2212 = $memory\sq_figure$rdmux[3][4][13]$a$2256'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][6]$2210' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][3]$a$2190 = $memory\sq_figure$rdmux[3][3][6]$b$2212'. Replacing $mux cell `$memory\sq_figure$rdmux[3][2][3]$2189' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][1][1]$b$2179 = $memory\sq_figure$rdmux[3][2][3]$a$2190'. Replacing $mux cell `$memory\sq_figure$rdmux[3][1][1]$2177' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][0][0]$b$2173 = $memory\sq_figure$rdmux[3][1][1]$b$2179'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][1]$2219' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][0]$b$2194 = $memory\sq_figure$rdmux[3][4][1]$a$2220'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][0]$2216' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][0]$a$2193 = $memory\sq_figure$rdmux[3][4][0]$a$2217'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][0]$2192' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][0]$a$2181 = $memory\sq_figure$rdmux[3][3][0]$b$2194'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][2]$2222' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][1]$a$2196 = $memory\sq_figure$rdmux[3][4][2]$a$2223'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][3]$2225' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][1]$b$2197 = $memory\sq_figure$rdmux[3][4][3]$a$2226'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][1]$2195' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][0]$b$2182 = $memory\sq_figure$rdmux[3][3][1]$b$2197'. Replacing $mux cell `$memory\sq_figure$rdmux[3][2][0]$2180' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][1][0]$a$2175 = $memory\sq_figure$rdmux[3][2][0]$a$2181'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][7]$2237' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][3]$b$2203 = $memory\sq_figure$rdmux[3][4][7]$a$2238'. Replacing $mux cell `$memory\sq_figure$rdmux[3][4][6]$2234' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][3][3]$a$2202 = $memory\sq_figure$rdmux[3][4][6]$a$2235'. Replacing $mux cell `$memory\sq_figure$rdmux[3][3][3]$2201' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][2][1]$b$2185 = $memory\sq_figure$rdmux[3][3][3]$b$2203'. Replacing $mux cell `$memory\sq_figure$rdmux[3][2][1]$2183' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][1][0]$b$2176 = $memory\sq_figure$rdmux[3][2][1]$a$2184'. Replacing $mux cell `$memory\sq_figure$rdmux[3][1][0]$2174' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[3][0][0]$a$2172 = $memory\sq_figure$rdmux[3][1][0]$b$2176'. Replacing $mux cell `$memory\sq_figure$rdmux[3][0][0]$2171' (0) in module `\top' with constant driver `$memrd$\sq_figure$example.v:308$182_DATA = $memory\sq_figure$rdmux[3][0][0]$a$2172'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][14]$2165' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][7]$a$2121 = $memory\sq_figure$rdmux[2][4][14]$b$2167'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][15]$2168' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][7]$b$2122 = $memory\sq_figure$rdmux[2][4][15]$b$2170'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][7]$2120' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][3]$b$2098 = $memory\sq_figure$rdmux[2][3][7]$a$2121'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][13]$2162' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][6]$b$2119 = $memory\sq_figure$rdmux[2][4][13]$b$2164'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][12]$2159' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][6]$a$2118 = $memory\sq_figure$rdmux[2][4][12]$b$2161'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][6]$2117' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][3]$a$2097 = $memory\sq_figure$rdmux[2][3][6]$a$2118'. Replacing $mux cell `$memory\sq_figure$rdmux[2][2][3]$2096' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][1][1]$b$2086 = $memory\sq_figure$rdmux[2][2][3]$a$2097'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][10]$2153' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][5]$a$2115 = $memory\sq_figure$rdmux[2][4][10]$b$2155'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][11]$2156' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][5]$b$2116 = $memory\sq_figure$rdmux[2][4][11]$b$2158'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][5]$2114' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][2]$b$2095 = $memory\sq_figure$rdmux[2][3][5]$a$2115'. Replacing $mux cell `$memory\sq_figure$rdmux[2][2][2]$2093' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][1][1]$a$2085 = $memory\sq_figure$rdmux[2][2][2]$a$2094'. Replacing $mux cell `$memory\sq_figure$rdmux[2][1][1]$2084' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][0][0]$b$2080 = $memory\sq_figure$rdmux[2][1][1]$b$2086'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][4]$2135' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][2]$a$2106 = $memory\sq_figure$rdmux[2][4][4]$b$2137'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][5]$2138' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][2]$b$2107 = $memory\sq_figure$rdmux[2][4][5]$b$2140'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][2]$2105' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][1]$a$2091 = $memory\sq_figure$rdmux[2][3][2]$a$2106'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][6]$2141' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][3]$a$2109 = $memory\sq_figure$rdmux[2][4][6]$b$2143'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][7]$2144' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][3]$b$2110 = $memory\sq_figure$rdmux[2][4][7]$b$2146'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][3]$2108' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][1]$b$2092 = $memory\sq_figure$rdmux[2][3][3]$a$2109'. Replacing $mux cell `$memory\sq_figure$rdmux[2][2][1]$2090' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][1][0]$b$2083 = $memory\sq_figure$rdmux[2][2][1]$a$2091'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][3]$2132' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][1]$b$2104 = $memory\sq_figure$rdmux[2][4][3]$b$2134'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][2]$2129' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][1]$a$2103 = $memory\sq_figure$rdmux[2][4][2]$b$2131'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][1]$2102' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][0]$b$2089 = $memory\sq_figure$rdmux[2][3][1]$a$2103'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][0]$2123' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][0]$a$2100 = $memory\sq_figure$rdmux[2][4][0]$b$2125'. Replacing $mux cell `$memory\sq_figure$rdmux[2][4][1]$2126' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][3][0]$b$2101 = $memory\sq_figure$rdmux[2][4][1]$b$2128'. Replacing $mux cell `$memory\sq_figure$rdmux[2][3][0]$2099' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][2][0]$a$2088 = $memory\sq_figure$rdmux[2][3][0]$a$2100'. Replacing $mux cell `$memory\sq_figure$rdmux[2][2][0]$2087' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][1][0]$a$2082 = $memory\sq_figure$rdmux[2][2][0]$a$2088'. Replacing $mux cell `$memory\sq_figure$rdmux[2][1][0]$2081' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[2][0][0]$a$2079 = $memory\sq_figure$rdmux[2][1][0]$b$2083'. Replacing $mux cell `$memory\sq_figure$rdmux[2][0][0]$2078' (0) in module `\top' with constant driver `$memrd$\sq_figure$example.v:307$180_DATA = $memory\sq_figure$rdmux[2][0][0]$a$2079'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2395' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2396 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2397' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2398 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][4][0]$2399' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][4][0]$y$2400 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2387' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2388 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2389' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2390 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][3][0]$2391' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][3][0]$y$2392 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2379' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2380 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2381' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2382 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][2][0]$2383' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][2][0]$y$2384 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2373' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2374 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][1][0]$2375' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][1][0]$y$2376 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][1][0]$2377' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][1][0]$y$2378 = $memory\sq_figure$wrmux[0][0][0]$y$2368'. Replacing $mux cell `$memory\sq_figure$wrmux[0][2][0]$2385' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][2][0]$y$2386 = $memory\sq_figure$wrmux[0][1][0]$y$2378'. Replacing $mux cell `$memory\sq_figure$wrmux[0][3][0]$2393' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][3][0]$y$2394 = $memory\sq_figure$wrmux[0][2][0]$y$2386'. Replacing $mux cell `$memory\sq_figure$wrmux[0][4][0]$2401' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][4][0]$y$2402 = $memory\sq_figure$wrmux[0][3][0]$y$2394'. Replacing $mux cell `$memory\sq_figure$rdmux[0][4][13]$1976' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][6]$b$1933 = $memory\sq_figure$rdmux[0][4][13]$a$1977'. Replacing $mux cell `$memory\sq_figure$rdmux[0][4][12]$1973' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][6]$a$1932 = $memory\sq_figure$rdmux[0][4][12]$a$1974'. Replacing $mux cell `$memory\sq_figure$rdmux[0][3][6]$1931' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][2][3]$a$1911 = $memory\sq_figure$rdmux[0][3][6]$a$1932'. Replacing $mux cell `$memory\sq_figure$rdmux[0][4][15]$1982' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][7]$b$1936 = $memory\sq_figure$rdmux[0][4][15]$a$1983'. Replacing $mux cell `$memory\sq_figure$rdmux[0][4][14]$1979' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][7]$a$1935 = $memory\sq_figure$rdmux[0][4][14]$a$1980'. Replacing $mux cell `$memory\sq_figure$rdmux[0][3][7]$1934' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][2][3]$b$1912 = $memory\sq_figure$rdmux[0][3][7]$a$1935'. Replacing $mux cell `$memory\sq_figure$rdmux[0][2][3]$1910' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][1][1]$b$1900 = $memory\sq_figure$rdmux[0][2][3]$a$1911'. Replacing $mux cell `$memory\sq_figure$rdmux[0][4][11]$1970' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][5]$b$1930 = $memory\sq_figure$rdmux[0][4][11]$a$1971'. Replacing $mux cell `$memory\sq_figure$rdmux[0][4][10]$1967' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][5]$a$1929 = $memory\sq_figure$rdmux[0][4][10]$a$1968'. Replacing $mux cell `$memory\sq_figure$rdmux[0][3][5]$1928' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][2][2]$b$1909 = $memory\sq_figure$rdmux[0][3][5]$a$1929'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][15]$2354' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][7]$b$2308 = $memory\sq_figure$rdmux[4][4][15]$b$2356'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][14]$2351' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][7]$a$2307 = $memory\sq_figure$rdmux[4][4][14]$b$2353'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][3]$2318' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][1]$b$2290 = $memory\sq_figure$rdmux[4][4][3]$b$2320'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][2]$2315' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][1]$a$2289 = $memory\sq_figure$rdmux[4][4][2]$b$2317'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][1]$2288' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][0]$b$2275 = $memory\sq_figure$rdmux[4][3][1]$b$2290'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][1]$2312' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][0]$b$2287 = $memory\sq_figure$rdmux[4][4][1]$b$2314'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][0]$2309' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][0]$a$2286 = $memory\sq_figure$rdmux[4][4][0]$b$2311'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][0]$2285' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][0]$a$2274 = $memory\sq_figure$rdmux[4][3][0]$b$2287'. Replacing $mux cell `$memory\sq_figure$rdmux[4][2][0]$2273' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][1][0]$a$2268 = $memory\sq_figure$rdmux[4][2][0]$a$2274'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][13]$2348' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][6]$b$2305 = $memory\sq_figure$rdmux[4][4][13]$b$2350'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][12]$2345' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][6]$a$2304 = $memory\sq_figure$rdmux[4][4][12]$b$2347'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][7]$2330' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][3]$b$2296 = $memory\sq_figure$rdmux[4][4][7]$b$2332'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][6]$2327' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][3]$a$2295 = $memory\sq_figure$rdmux[4][4][6]$b$2329'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][3]$2294' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][1]$b$2278 = $memory\sq_figure$rdmux[4][3][3]$b$2296'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][5]$2324' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][2]$b$2293 = $memory\sq_figure$rdmux[4][4][5]$b$2326'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][4]$2321' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][2]$a$2292 = $memory\sq_figure$rdmux[4][4][4]$b$2323'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][2]$2291' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][1]$a$2277 = $memory\sq_figure$rdmux[4][3][2]$b$2293'. Replacing $mux cell `$memory\sq_figure$rdmux[4][2][1]$2276' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][1][0]$b$2269 = $memory\sq_figure$rdmux[4][2][1]$a$2277'. Replacing $mux cell `$memory\sq_figure$rdmux[4][1][0]$2267' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][0][0]$a$2265 = $memory\sq_figure$rdmux[4][1][0]$b$2269'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][7]$2306' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][3]$b$2284 = $memory\sq_figure$rdmux[4][3][7]$b$2308'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][6]$2303' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][3]$a$2283 = $memory\sq_figure$rdmux[4][3][6]$b$2305'. Replacing $mux cell `$memory\sq_figure$rdmux[4][2][3]$2282' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][1][1]$b$2272 = $memory\sq_figure$rdmux[4][2][3]$a$2283'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][11]$2342' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][5]$b$2302 = $memory\sq_figure$rdmux[4][4][11]$b$2344'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][10]$2339' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][5]$a$2301 = $memory\sq_figure$rdmux[4][4][10]$b$2341'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][5]$2300' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][2]$b$2281 = $memory\sq_figure$rdmux[4][3][5]$b$2302'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][9]$2336' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][4]$b$2299 = $memory\sq_figure$rdmux[4][4][9]$b$2338'. Replacing $mux cell `$memory\sq_figure$rdmux[4][4][8]$2333' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][3][4]$a$2298 = $memory\sq_figure$rdmux[4][4][8]$b$2335'. Replacing $mux cell `$memory\sq_figure$rdmux[4][3][4]$2297' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][2][2]$a$2280 = $memory\sq_figure$rdmux[4][3][4]$b$2299'. Replacing $mux cell `$memory\sq_figure$rdmux[4][2][2]$2279' (0) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][1][1]$a$2271 = $memory\sq_figure$rdmux[4][2][2]$a$2280'. Replacing $mux cell `$memory\sq_figure$rdmux[4][1][1]$2270' (1) in module `\top' with constant driver `$memory\sq_figure$rdmux[4][0][0]$b$2266 = $memory\sq_figure$rdmux[4][1][1]$b$2272'. Replacing $mux cell `$memory\sq_figure$rdmux[4][0][0]$2264' (0) in module `\top' with constant driver `$memrd$\sq_figure$example.v:309$184_DATA = $memory\sq_figure$rdmux[4][0][0]$a$2265'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2403' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2404 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][5][0]$2405' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][5][0]$y$2406 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][5][0]$2407' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][5][0]$y$2408 = $memory\sq_figure$wrmux[0][4][0]$y$2402'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2409' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2410 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][6][0]$2411' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][6][0]$y$2412 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][6][0]$2413' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][6][0]$y$2414 = $memory\sq_figure$wrmux[0][5][0]$y$2408'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2415' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2416 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][7][0]$2417' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][7][0]$y$2418 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][7][0]$2419' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][7][0]$y$2420 = $memory\sq_figure$wrmux[0][6][0]$y$2414'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2421' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2422 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2423' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2424 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][8][0]$2425' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][8][0]$y$2426 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][8][0]$2427' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][8][0]$y$2428 = $memory\sq_figure$wrmux[0][7][0]$y$2420'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2429' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2430 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][9][0]$2431' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][9][0]$y$2432 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][9][0]$2433' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][9][0]$y$2434 = $memory\sq_figure$wrmux[0][8][0]$y$2428'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2435' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2436 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][10][0]$2437' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][10][0]$y$2438 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][10][0]$2439' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][10][0]$y$2440 = $memory\sq_figure$wrmux[0][9][0]$y$2434'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2441' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2442 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][11][0]$2443' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][11][0]$y$2444 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][11][0]$2445' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][11][0]$y$2446 = $memory\sq_figure$wrmux[0][10][0]$y$2440'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2447' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2448 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2449' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2450 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][12][0]$2451' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][12][0]$y$2452 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][12][0]$2453' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][12][0]$y$2454 = $memory\sq_figure$wrmux[0][11][0]$y$2446'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2455' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2456 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][13][0]$2457' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][13][0]$y$2458 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][13][0]$2459' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][13][0]$y$2460 = $memory\sq_figure$wrmux[0][12][0]$y$2454'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2461' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2462 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][14][0]$2463' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][14][0]$y$2464 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][14][0]$2465' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][14][0]$y$2466 = $memory\sq_figure$wrmux[0][13][0]$y$2460'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2467' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2468 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][15][0]$2469' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][15][0]$y$2470 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][15][0]$2471' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][15][0]$y$2472 = $memory\sq_figure$wrmux[0][14][0]$y$2466'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2473' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2474 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2475' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2476 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][16][0]$2477' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][16][0]$y$2478 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][16][0]$2479' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][16][0]$y$2480 = $memory\sq_figure$wrmux[0][15][0]$y$2472'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2481' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2482 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][17][0]$2483' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][17][0]$y$2484 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][17][0]$2485' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][17][0]$y$2486 = $memory\sq_figure$wrmux[0][16][0]$y$2480'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2487' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2488 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][18][0]$2489' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][18][0]$y$2490 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][18][0]$2491' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][18][0]$y$2492 = $memory\sq_figure$wrmux[0][17][0]$y$2486'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2493' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2494 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[0][19][0]$2495' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[0][19][0]$y$2496 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[0][19][0]$2497' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[0][19][0]$y$2498 = $memory\sq_figure$wrmux[0][18][0]$y$2492'. Replacing $eq cell `$auto$memory_map.cc:65:addr_decode$2499' (isneq) in module `\top' with constant driver `$auto$rtlil.cc:1709:Eq$2500 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2501' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2502 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2503' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2504 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][0][0]$2505' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][0][0]$y$2506 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][0][0]$2507' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][0][0]$y$2508 = \sq_figure[1]'. Replacing $eq cell `$auto$memory_map.cc:65:addr_decode$2509' (empty) in module `\top' with constant driver `$auto$rtlil.cc:1709:Eq$2510 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2511' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2512 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2513' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2514 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[1][1][0]$2515' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[1][1][0]$y$2516 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2519' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2520 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2521' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2522 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][2][0]$2523' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][2][0]$y$2524 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][2][0]$2525' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][2][0]$y$2526 = $memory\sq_figure$wrmux[1][1][0]$y$2518'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2527' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2528 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2529' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2530 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][3][0]$2531' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][3][0]$y$2532 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][3][0]$2533' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][3][0]$y$2534 = $memory\sq_figure$wrmux[1][2][0]$y$2526'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2535' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2536 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][4][0]$2537' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][4][0]$y$2538 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][4][0]$2539' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][4][0]$y$2540 = $memory\sq_figure$wrmux[1][3][0]$y$2534'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2541' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2542 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][5][0]$2543' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][5][0]$y$2544 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][5][0]$2545' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][5][0]$y$2546 = $memory\sq_figure$wrmux[1][4][0]$y$2540'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2547' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2548 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][6][0]$2549' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][6][0]$y$2550 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][6][0]$2551' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][6][0]$y$2552 = $memory\sq_figure$wrmux[1][5][0]$y$2546'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2553' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2554 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][7][0]$2555' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][7][0]$y$2556 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][7][0]$2557' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][7][0]$y$2558 = $memory\sq_figure$wrmux[1][6][0]$y$2552'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2559' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2560 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][8][0]$2561' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][8][0]$y$2562 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][8][0]$2563' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][8][0]$y$2564 = $memory\sq_figure$wrmux[1][7][0]$y$2558'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2565' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2566 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][9][0]$2567' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][9][0]$y$2568 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][9][0]$2569' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][9][0]$y$2570 = $memory\sq_figure$wrmux[1][8][0]$y$2564'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2571' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2572 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][10][0]$2573' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][10][0]$y$2574 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][10][0]$2575' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][10][0]$y$2576 = $memory\sq_figure$wrmux[1][9][0]$y$2570'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2577' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2578 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][11][0]$2579' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][11][0]$y$2580 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][11][0]$2581' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][11][0]$y$2582 = $memory\sq_figure$wrmux[1][10][0]$y$2576'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2583' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2584 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][12][0]$2585' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][12][0]$y$2586 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][12][0]$2587' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][12][0]$y$2588 = $memory\sq_figure$wrmux[1][11][0]$y$2582'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2589' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2590 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][13][0]$2591' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][13][0]$y$2592 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][13][0]$2593' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][13][0]$y$2594 = $memory\sq_figure$wrmux[1][12][0]$y$2588'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2595' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2596 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][14][0]$2597' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][14][0]$y$2598 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][14][0]$2599' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][14][0]$y$2600 = $memory\sq_figure$wrmux[1][13][0]$y$2594'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2601' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2602 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][15][0]$2603' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][15][0]$y$2604 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][15][0]$2605' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][15][0]$y$2606 = $memory\sq_figure$wrmux[1][14][0]$y$2600'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2607' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2608 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][16][0]$2609' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][16][0]$y$2610 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][16][0]$2611' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][16][0]$y$2612 = $memory\sq_figure$wrmux[1][15][0]$y$2606'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2613' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2614 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][17][0]$2615' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][17][0]$y$2616 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][17][0]$2617' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][17][0]$y$2618 = $memory\sq_figure$wrmux[1][16][0]$y$2612'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2619' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2620 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][18][0]$2621' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][18][0]$y$2622 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][18][0]$2623' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][18][0]$y$2624 = $memory\sq_figure$wrmux[1][17][0]$y$2618'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2625' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2626 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[1][19][0]$2627' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[1][19][0]$y$2628 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[1][19][0]$2629' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[1][19][0]$y$2630 = $memory\sq_figure$wrmux[1][18][0]$y$2624'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2631' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2632 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2633' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2634 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][0][0]$2635' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][0][0]$y$2636 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][0][0]$2637' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][0][0]$y$2638 = \sq_figure[2]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2639' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2640 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2641' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2642 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][1][0]$2643' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][1][0]$y$2644 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][1][0]$2645' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][1][0]$y$2646 = $memory\sq_figure$wrmux[2][0][0]$y$2638'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2647' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2648 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2649' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2650 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[2][2][0]$2651' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[2][2][0]$y$2652 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2655' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2656 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2657' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2658 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][3][0]$2659' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][3][0]$y$2660 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][3][0]$2661' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][3][0]$y$2662 = $memory\sq_figure$wrmux[2][2][0]$y$2654'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2663' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2664 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][4][0]$2665' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][4][0]$y$2666 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][4][0]$2667' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][4][0]$y$2668 = $memory\sq_figure$wrmux[2][3][0]$y$2662'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2669' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2670 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][5][0]$2671' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][5][0]$y$2672 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][5][0]$2673' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][5][0]$y$2674 = $memory\sq_figure$wrmux[2][4][0]$y$2668'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2675' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2676 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][6][0]$2677' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][6][0]$y$2678 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][6][0]$2679' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][6][0]$y$2680 = $memory\sq_figure$wrmux[2][5][0]$y$2674'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2681' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2682 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][7][0]$2683' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][7][0]$y$2684 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][7][0]$2685' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][7][0]$y$2686 = $memory\sq_figure$wrmux[2][6][0]$y$2680'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2687' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2688 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][8][0]$2689' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][8][0]$y$2690 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][8][0]$2691' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][8][0]$y$2692 = $memory\sq_figure$wrmux[2][7][0]$y$2686'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2693' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2694 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][9][0]$2695' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][9][0]$y$2696 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][9][0]$2697' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][9][0]$y$2698 = $memory\sq_figure$wrmux[2][8][0]$y$2692'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2699' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2700 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][10][0]$2701' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][10][0]$y$2702 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][10][0]$2703' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][10][0]$y$2704 = $memory\sq_figure$wrmux[2][9][0]$y$2698'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2705' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2706 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][11][0]$2707' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][11][0]$y$2708 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][11][0]$2709' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][11][0]$y$2710 = $memory\sq_figure$wrmux[2][10][0]$y$2704'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2711' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2712 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][12][0]$2713' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][12][0]$y$2714 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][12][0]$2715' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][12][0]$y$2716 = $memory\sq_figure$wrmux[2][11][0]$y$2710'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2717' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2718 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][13][0]$2719' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][13][0]$y$2720 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][13][0]$2721' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][13][0]$y$2722 = $memory\sq_figure$wrmux[2][12][0]$y$2716'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2723' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2724 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][14][0]$2725' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][14][0]$y$2726 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][14][0]$2727' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][14][0]$y$2728 = $memory\sq_figure$wrmux[2][13][0]$y$2722'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2729' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2730 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][15][0]$2731' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][15][0]$y$2732 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][15][0]$2733' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][15][0]$y$2734 = $memory\sq_figure$wrmux[2][14][0]$y$2728'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2735' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2736 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][16][0]$2737' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][16][0]$y$2738 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][16][0]$2739' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][16][0]$y$2740 = $memory\sq_figure$wrmux[2][15][0]$y$2734'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2741' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2742 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][17][0]$2743' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][17][0]$y$2744 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][17][0]$2745' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][17][0]$y$2746 = $memory\sq_figure$wrmux[2][16][0]$y$2740'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2747' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2748 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][18][0]$2749' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][18][0]$y$2750 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][18][0]$2751' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][18][0]$y$2752 = $memory\sq_figure$wrmux[2][17][0]$y$2746'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2753' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2754 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[2][19][0]$2755' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[2][19][0]$y$2756 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[2][19][0]$2757' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[2][19][0]$y$2758 = $memory\sq_figure$wrmux[2][18][0]$y$2752'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2759' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2760 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2761' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2762 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][0][0]$2763' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][0][0]$y$2764 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][0][0]$2765' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][0][0]$y$2766 = \sq_figure[3]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2767' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2768 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2769' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2770 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][1][0]$2771' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][1][0]$y$2772 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][1][0]$2773' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][1][0]$y$2774 = $memory\sq_figure$wrmux[3][0][0]$y$2766'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2775' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2776 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2777' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2778 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][2][0]$2779' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][2][0]$y$2780 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][2][0]$2781' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][2][0]$y$2782 = $memory\sq_figure$wrmux[3][1][0]$y$2774'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2783' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2784 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2785' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2786 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[3][3][0]$2787' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[3][3][0]$y$2788 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2791' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2792 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][4][0]$2793' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][4][0]$y$2794 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][4][0]$2795' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][4][0]$y$2796 = $memory\sq_figure$wrmux[3][3][0]$y$2790'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2797' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2798 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][5][0]$2799' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][5][0]$y$2800 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][5][0]$2801' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][5][0]$y$2802 = $memory\sq_figure$wrmux[3][4][0]$y$2796'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2803' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2804 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][6][0]$2805' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][6][0]$y$2806 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][6][0]$2807' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][6][0]$y$2808 = $memory\sq_figure$wrmux[3][5][0]$y$2802'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2809' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2810 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][7][0]$2811' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][7][0]$y$2812 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][7][0]$2813' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][7][0]$y$2814 = $memory\sq_figure$wrmux[3][6][0]$y$2808'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2815' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2816 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][8][0]$2817' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][8][0]$y$2818 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][8][0]$2819' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][8][0]$y$2820 = $memory\sq_figure$wrmux[3][7][0]$y$2814'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2821' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2822 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][9][0]$2823' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][9][0]$y$2824 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][9][0]$2825' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][9][0]$y$2826 = $memory\sq_figure$wrmux[3][8][0]$y$2820'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2827' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2828 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][10][0]$2829' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][10][0]$y$2830 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][10][0]$2831' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][10][0]$y$2832 = $memory\sq_figure$wrmux[3][9][0]$y$2826'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2833' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2834 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][11][0]$2835' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][11][0]$y$2836 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][11][0]$2837' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][11][0]$y$2838 = $memory\sq_figure$wrmux[3][10][0]$y$2832'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2839' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2840 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][12][0]$2841' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][12][0]$y$2842 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][12][0]$2843' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][12][0]$y$2844 = $memory\sq_figure$wrmux[3][11][0]$y$2838'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2845' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2846 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][13][0]$2847' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][13][0]$y$2848 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][13][0]$2849' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][13][0]$y$2850 = $memory\sq_figure$wrmux[3][12][0]$y$2844'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2851' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2852 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][14][0]$2853' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][14][0]$y$2854 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][14][0]$2855' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][14][0]$y$2856 = $memory\sq_figure$wrmux[3][13][0]$y$2850'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2857' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2858 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][15][0]$2859' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][15][0]$y$2860 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][15][0]$2861' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][15][0]$y$2862 = $memory\sq_figure$wrmux[3][14][0]$y$2856'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2863' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2864 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][16][0]$2865' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][16][0]$y$2866 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][16][0]$2867' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][16][0]$y$2868 = $memory\sq_figure$wrmux[3][15][0]$y$2862'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2869' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2870 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][17][0]$2871' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][17][0]$y$2872 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][17][0]$2873' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][17][0]$y$2874 = $memory\sq_figure$wrmux[3][16][0]$y$2868'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2875' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2876 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][18][0]$2877' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][18][0]$y$2878 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][18][0]$2879' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][18][0]$y$2880 = $memory\sq_figure$wrmux[3][17][0]$y$2874'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2881' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2882 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[3][19][0]$2883' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[3][19][0]$y$2884 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[3][19][0]$2885' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[3][19][0]$y$2886 = $memory\sq_figure$wrmux[3][18][0]$y$2880'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2887' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2888 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2889' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2890 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][0][0]$2891' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][0][0]$y$2892 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][0][0]$2893' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][0][0]$y$2894 = \sq_figure[4]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2895' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2896 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][1][0]$2897' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][1][0]$y$2898 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][1][0]$2899' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][1][0]$y$2900 = $memory\sq_figure$wrmux[4][0][0]$y$2894'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2901' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2902 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][2][0]$2903' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][2][0]$y$2904 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][2][0]$2905' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][2][0]$y$2906 = $memory\sq_figure$wrmux[4][1][0]$y$2900'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2907' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2908 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][3][0]$2909' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][3][0]$y$2910 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][3][0]$2911' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][3][0]$y$2912 = $memory\sq_figure$wrmux[4][2][0]$y$2906'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2913' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2914 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2915' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2916 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[4][4][0]$2917' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[4][4][0]$y$2918 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2921' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2922 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][5][0]$2923' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][5][0]$y$2924 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][5][0]$2925' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][5][0]$y$2926 = $memory\sq_figure$wrmux[4][4][0]$y$2920'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2927' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2928 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][6][0]$2929' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][6][0]$y$2930 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][6][0]$2931' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][6][0]$y$2932 = $memory\sq_figure$wrmux[4][5][0]$y$2926'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2933' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2934 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][7][0]$2935' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][7][0]$y$2936 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][7][0]$2937' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][7][0]$y$2938 = $memory\sq_figure$wrmux[4][6][0]$y$2932'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2939' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2940 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2941' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2942 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][8][0]$2943' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][8][0]$y$2944 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][8][0]$2945' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][8][0]$y$2946 = $memory\sq_figure$wrmux[4][7][0]$y$2938'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2947' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2948 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][9][0]$2949' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][9][0]$y$2950 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][9][0]$2951' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][9][0]$y$2952 = $memory\sq_figure$wrmux[4][8][0]$y$2946'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2953' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2954 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][10][0]$2955' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][10][0]$y$2956 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][10][0]$2957' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][10][0]$y$2958 = $memory\sq_figure$wrmux[4][9][0]$y$2952'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2959' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2960 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][11][0]$2961' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][11][0]$y$2962 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][11][0]$2963' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][11][0]$y$2964 = $memory\sq_figure$wrmux[4][10][0]$y$2958'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2965' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2966 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2967' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2968 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][12][0]$2969' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][12][0]$y$2970 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][12][0]$2971' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][12][0]$y$2972 = $memory\sq_figure$wrmux[4][11][0]$y$2964'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2973' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2974 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][13][0]$2975' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][13][0]$y$2976 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][13][0]$2977' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][13][0]$y$2978 = $memory\sq_figure$wrmux[4][12][0]$y$2972'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2979' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2980 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][14][0]$2981' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][14][0]$y$2982 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][14][0]$2983' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][14][0]$y$2984 = $memory\sq_figure$wrmux[4][13][0]$y$2978'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2985' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2986 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][15][0]$2987' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][15][0]$y$2988 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][15][0]$2989' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][15][0]$y$2990 = $memory\sq_figure$wrmux[4][14][0]$y$2984'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2991' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2992 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2993' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$2994 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][16][0]$2995' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][16][0]$y$2996 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][16][0]$2997' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][16][0]$y$2998 = $memory\sq_figure$wrmux[4][15][0]$y$2990'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$2999' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3000 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][17][0]$3001' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][17][0]$y$3002 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][17][0]$3003' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][17][0]$y$3004 = $memory\sq_figure$wrmux[4][16][0]$y$2998'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3005' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3006 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][18][0]$3007' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][18][0]$y$3008 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][18][0]$3009' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][18][0]$y$3010 = $memory\sq_figure$wrmux[4][17][0]$y$3004'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3011' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3012 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[4][19][0]$3013' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[4][19][0]$y$3014 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[4][19][0]$3015' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[4][19][0]$y$3016 = $memory\sq_figure$wrmux[4][18][0]$y$3010'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3017' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3018 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][0][0]$3019' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][0][0]$y$3020 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][0][0]$3021' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][0][0]$y$3022 = \sq_figure[5]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3023' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3024 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][1][0]$3025' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][1][0]$y$3026 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][1][0]$3027' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][1][0]$y$3028 = $memory\sq_figure$wrmux[5][0][0]$y$3022'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3029' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3030 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][2][0]$3031' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][2][0]$y$3032 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][2][0]$3033' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][2][0]$y$3034 = $memory\sq_figure$wrmux[5][1][0]$y$3028'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3035' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3036 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][3][0]$3037' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][3][0]$y$3038 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][3][0]$3039' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][3][0]$y$3040 = $memory\sq_figure$wrmux[5][2][0]$y$3034'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3041' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3042 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][4][0]$3043' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][4][0]$y$3044 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][4][0]$3045' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][4][0]$y$3046 = $memory\sq_figure$wrmux[5][3][0]$y$3040'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3047' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3048 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[5][5][0]$3049' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[5][5][0]$y$3050 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3053' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3054 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][6][0]$3055' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][6][0]$y$3056 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][6][0]$3057' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][6][0]$y$3058 = $memory\sq_figure$wrmux[5][5][0]$y$3052'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3059' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3060 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][7][0]$3061' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][7][0]$y$3062 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][7][0]$3063' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][7][0]$y$3064 = $memory\sq_figure$wrmux[5][6][0]$y$3058'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3065' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3066 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][8][0]$3067' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][8][0]$y$3068 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][8][0]$3069' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][8][0]$y$3070 = $memory\sq_figure$wrmux[5][7][0]$y$3064'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3071' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3072 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][9][0]$3073' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][9][0]$y$3074 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][9][0]$3075' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][9][0]$y$3076 = $memory\sq_figure$wrmux[5][8][0]$y$3070'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3077' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3078 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][10][0]$3079' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][10][0]$y$3080 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][10][0]$3081' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][10][0]$y$3082 = $memory\sq_figure$wrmux[5][9][0]$y$3076'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3083' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3084 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][11][0]$3085' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][11][0]$y$3086 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][11][0]$3087' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][11][0]$y$3088 = $memory\sq_figure$wrmux[5][10][0]$y$3082'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3089' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3090 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][12][0]$3091' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][12][0]$y$3092 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][12][0]$3093' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][12][0]$y$3094 = $memory\sq_figure$wrmux[5][11][0]$y$3088'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3095' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3096 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][13][0]$3097' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][13][0]$y$3098 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][13][0]$3099' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][13][0]$y$3100 = $memory\sq_figure$wrmux[5][12][0]$y$3094'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3101' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3102 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][14][0]$3103' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][14][0]$y$3104 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][14][0]$3105' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][14][0]$y$3106 = $memory\sq_figure$wrmux[5][13][0]$y$3100'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3107' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3108 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][15][0]$3109' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][15][0]$y$3110 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][15][0]$3111' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][15][0]$y$3112 = $memory\sq_figure$wrmux[5][14][0]$y$3106'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3113' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3114 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][16][0]$3115' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][16][0]$y$3116 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][16][0]$3117' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][16][0]$y$3118 = $memory\sq_figure$wrmux[5][15][0]$y$3112'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3119' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3120 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][17][0]$3121' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][17][0]$y$3122 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][17][0]$3123' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][17][0]$y$3124 = $memory\sq_figure$wrmux[5][16][0]$y$3118'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3125' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3126 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][18][0]$3127' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][18][0]$y$3128 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][18][0]$3129' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][18][0]$y$3130 = $memory\sq_figure$wrmux[5][17][0]$y$3124'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3131' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3132 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[5][19][0]$3133' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[5][19][0]$y$3134 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[5][19][0]$3135' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[5][19][0]$y$3136 = $memory\sq_figure$wrmux[5][18][0]$y$3130'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3137' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3138 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][0][0]$3139' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][0][0]$y$3140 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][0][0]$3141' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][0][0]$y$3142 = \sq_figure[6]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3143' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3144 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][1][0]$3145' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][1][0]$y$3146 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][1][0]$3147' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][1][0]$y$3148 = $memory\sq_figure$wrmux[6][0][0]$y$3142'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3149' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3150 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][2][0]$3151' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][2][0]$y$3152 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][2][0]$3153' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][2][0]$y$3154 = $memory\sq_figure$wrmux[6][1][0]$y$3148'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3155' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3156 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][3][0]$3157' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][3][0]$y$3158 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][3][0]$3159' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][3][0]$y$3160 = $memory\sq_figure$wrmux[6][2][0]$y$3154'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3161' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3162 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][4][0]$3163' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][4][0]$y$3164 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][4][0]$3165' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][4][0]$y$3166 = $memory\sq_figure$wrmux[6][3][0]$y$3160'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3167' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3168 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][5][0]$3169' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][5][0]$y$3170 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][5][0]$3171' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][5][0]$y$3172 = $memory\sq_figure$wrmux[6][4][0]$y$3166'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3173' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3174 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[6][6][0]$3175' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[6][6][0]$y$3176 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3179' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3180 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][7][0]$3181' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][7][0]$y$3182 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][7][0]$3183' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][7][0]$y$3184 = $memory\sq_figure$wrmux[6][6][0]$y$3178'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3185' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3186 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][8][0]$3187' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][8][0]$y$3188 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][8][0]$3189' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][8][0]$y$3190 = $memory\sq_figure$wrmux[6][7][0]$y$3184'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3191' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3192 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][9][0]$3193' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][9][0]$y$3194 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][9][0]$3195' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][9][0]$y$3196 = $memory\sq_figure$wrmux[6][8][0]$y$3190'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3197' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3198 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][10][0]$3199' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][10][0]$y$3200 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][10][0]$3201' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][10][0]$y$3202 = $memory\sq_figure$wrmux[6][9][0]$y$3196'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3203' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3204 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][11][0]$3205' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][11][0]$y$3206 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][11][0]$3207' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][11][0]$y$3208 = $memory\sq_figure$wrmux[6][10][0]$y$3202'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3209' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3210 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][12][0]$3211' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][12][0]$y$3212 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][12][0]$3213' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][12][0]$y$3214 = $memory\sq_figure$wrmux[6][11][0]$y$3208'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3215' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3216 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][13][0]$3217' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][13][0]$y$3218 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][13][0]$3219' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][13][0]$y$3220 = $memory\sq_figure$wrmux[6][12][0]$y$3214'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3221' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3222 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][14][0]$3223' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][14][0]$y$3224 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][14][0]$3225' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][14][0]$y$3226 = $memory\sq_figure$wrmux[6][13][0]$y$3220'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3227' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3228 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][15][0]$3229' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][15][0]$y$3230 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][15][0]$3231' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][15][0]$y$3232 = $memory\sq_figure$wrmux[6][14][0]$y$3226'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3233' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3234 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][16][0]$3235' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][16][0]$y$3236 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][16][0]$3237' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][16][0]$y$3238 = $memory\sq_figure$wrmux[6][15][0]$y$3232'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3239' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3240 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][17][0]$3241' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][17][0]$y$3242 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][17][0]$3243' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][17][0]$y$3244 = $memory\sq_figure$wrmux[6][16][0]$y$3238'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3245' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3246 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][18][0]$3247' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][18][0]$y$3248 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][18][0]$3249' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][18][0]$y$3250 = $memory\sq_figure$wrmux[6][17][0]$y$3244'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3251' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3252 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[6][19][0]$3253' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[6][19][0]$y$3254 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[6][19][0]$3255' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[6][19][0]$y$3256 = $memory\sq_figure$wrmux[6][18][0]$y$3250'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3257' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3258 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][0][0]$3259' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][0][0]$y$3260 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][0][0]$3261' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][0][0]$y$3262 = \sq_figure[7]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3263' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3264 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][1][0]$3265' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][1][0]$y$3266 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][1][0]$3267' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][1][0]$y$3268 = $memory\sq_figure$wrmux[7][0][0]$y$3262'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3269' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3270 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][2][0]$3271' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][2][0]$y$3272 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][2][0]$3273' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][2][0]$y$3274 = $memory\sq_figure$wrmux[7][1][0]$y$3268'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3275' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3276 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][3][0]$3277' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][3][0]$y$3278 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][3][0]$3279' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][3][0]$y$3280 = $memory\sq_figure$wrmux[7][2][0]$y$3274'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3281' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3282 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][4][0]$3283' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][4][0]$y$3284 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][4][0]$3285' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][4][0]$y$3286 = $memory\sq_figure$wrmux[7][3][0]$y$3280'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3287' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3288 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][5][0]$3289' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][5][0]$y$3290 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][5][0]$3291' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][5][0]$y$3292 = $memory\sq_figure$wrmux[7][4][0]$y$3286'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3293' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3294 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][6][0]$3295' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][6][0]$y$3296 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][6][0]$3297' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][6][0]$y$3298 = $memory\sq_figure$wrmux[7][5][0]$y$3292'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3299' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3300 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[7][7][0]$3301' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[7][7][0]$y$3302 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3305' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3306 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][8][0]$3307' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][8][0]$y$3308 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][8][0]$3309' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][8][0]$y$3310 = $memory\sq_figure$wrmux[7][7][0]$y$3304'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3311' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3312 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][9][0]$3313' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][9][0]$y$3314 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][9][0]$3315' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][9][0]$y$3316 = $memory\sq_figure$wrmux[7][8][0]$y$3310'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3317' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3318 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][10][0]$3319' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][10][0]$y$3320 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][10][0]$3321' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][10][0]$y$3322 = $memory\sq_figure$wrmux[7][9][0]$y$3316'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3323' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3324 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][11][0]$3325' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][11][0]$y$3326 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][11][0]$3327' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][11][0]$y$3328 = $memory\sq_figure$wrmux[7][10][0]$y$3322'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3329' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3330 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][12][0]$3331' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][12][0]$y$3332 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][12][0]$3333' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][12][0]$y$3334 = $memory\sq_figure$wrmux[7][11][0]$y$3328'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3335' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3336 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][13][0]$3337' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][13][0]$y$3338 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][13][0]$3339' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][13][0]$y$3340 = $memory\sq_figure$wrmux[7][12][0]$y$3334'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3341' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3342 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][14][0]$3343' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][14][0]$y$3344 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][14][0]$3345' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][14][0]$y$3346 = $memory\sq_figure$wrmux[7][13][0]$y$3340'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3347' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3348 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][15][0]$3349' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][15][0]$y$3350 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][15][0]$3351' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][15][0]$y$3352 = $memory\sq_figure$wrmux[7][14][0]$y$3346'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3353' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3354 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][16][0]$3355' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][16][0]$y$3356 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][16][0]$3357' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][16][0]$y$3358 = $memory\sq_figure$wrmux[7][15][0]$y$3352'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3359' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3360 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][17][0]$3361' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][17][0]$y$3362 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][17][0]$3363' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][17][0]$y$3364 = $memory\sq_figure$wrmux[7][16][0]$y$3358'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3365' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3366 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][18][0]$3367' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][18][0]$y$3368 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][18][0]$3369' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][18][0]$y$3370 = $memory\sq_figure$wrmux[7][17][0]$y$3364'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3371' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3372 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[7][19][0]$3373' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[7][19][0]$y$3374 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[7][19][0]$3375' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[7][19][0]$y$3376 = $memory\sq_figure$wrmux[7][18][0]$y$3370'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3377' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3378 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3379' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3380 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][0][0]$3381' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][0][0]$y$3382 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][0][0]$3383' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][0][0]$y$3384 = \sq_figure[8]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3385' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3386 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][1][0]$3387' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][1][0]$y$3388 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][1][0]$3389' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][1][0]$y$3390 = $memory\sq_figure$wrmux[8][0][0]$y$3384'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3391' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3392 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][2][0]$3393' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][2][0]$y$3394 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][2][0]$3395' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][2][0]$y$3396 = $memory\sq_figure$wrmux[8][1][0]$y$3390'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3397' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3398 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][3][0]$3399' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][3][0]$y$3400 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][3][0]$3401' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][3][0]$y$3402 = $memory\sq_figure$wrmux[8][2][0]$y$3396'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3403' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3404 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3405' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3406 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][4][0]$3407' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][4][0]$y$3408 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][4][0]$3409' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][4][0]$y$3410 = $memory\sq_figure$wrmux[8][3][0]$y$3402'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3411' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3412 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][5][0]$3413' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][5][0]$y$3414 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][5][0]$3415' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][5][0]$y$3416 = $memory\sq_figure$wrmux[8][4][0]$y$3410'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3417' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3418 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][6][0]$3419' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][6][0]$y$3420 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][6][0]$3421' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][6][0]$y$3422 = $memory\sq_figure$wrmux[8][5][0]$y$3416'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3423' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3424 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][7][0]$3425' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][7][0]$y$3426 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][7][0]$3427' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][7][0]$y$3428 = $memory\sq_figure$wrmux[8][6][0]$y$3422'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3429' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3430 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3431' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3432 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][8][0]$3433' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][8][0]$y$3434 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][8][0]$3435' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][8][0]$y$3436 = $memory\sq_figure$wrmux[8][7][0]$y$3428'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3437' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3438 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][9][0]$3439' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][9][0]$y$3440 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][9][0]$3441' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][9][0]$y$3442 = $memory\sq_figure$wrmux[8][8][0]$y$3436'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3443' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3444 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][10][0]$3445' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][10][0]$y$3446 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][10][0]$3447' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][10][0]$y$3448 = $memory\sq_figure$wrmux[8][9][0]$y$3442'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3449' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3450 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][11][0]$3451' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][11][0]$y$3452 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][11][0]$3453' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][11][0]$y$3454 = $memory\sq_figure$wrmux[8][10][0]$y$3448'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3455' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3456 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3457' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3458 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][12][0]$3459' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][12][0]$y$3460 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][12][0]$3461' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][12][0]$y$3462 = $memory\sq_figure$wrmux[8][11][0]$y$3454'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3463' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3464 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][13][0]$3465' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][13][0]$y$3466 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][13][0]$3467' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][13][0]$y$3468 = $memory\sq_figure$wrmux[8][12][0]$y$3462'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3469' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3470 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][14][0]$3471' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][14][0]$y$3472 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][14][0]$3473' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][14][0]$y$3474 = $memory\sq_figure$wrmux[8][13][0]$y$3468'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3475' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3476 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][15][0]$3477' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][15][0]$y$3478 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][15][0]$3479' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][15][0]$y$3480 = $memory\sq_figure$wrmux[8][14][0]$y$3474'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3481' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3482 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3483' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3484 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[8][16][0]$3485' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[8][16][0]$y$3486 = $auto$rtlil.cc:1698:Or$1369'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3489' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3490 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][17][0]$3491' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][17][0]$y$3492 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][17][0]$3493' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][17][0]$y$3494 = $memory\sq_figure$wrmux[8][16][0]$y$3488'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3495' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3496 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][18][0]$3497' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][18][0]$y$3498 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][18][0]$3499' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][18][0]$y$3500 = $memory\sq_figure$wrmux[8][17][0]$y$3494'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3501' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3502 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[8][19][0]$3503' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[8][19][0]$y$3504 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[8][19][0]$3505' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[8][19][0]$y$3506 = $memory\sq_figure$wrmux[8][18][0]$y$3500'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3507' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3508 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][0][0]$3509' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][0][0]$y$3510 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][0][0]$3511' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][0][0]$y$3512 = \sq_figure[9]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3513' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3514 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][1][0]$3515' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][1][0]$y$3516 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][1][0]$3517' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][1][0]$y$3518 = $memory\sq_figure$wrmux[9][0][0]$y$3512'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3519' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3520 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][2][0]$3521' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][2][0]$y$3522 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][2][0]$3523' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][2][0]$y$3524 = $memory\sq_figure$wrmux[9][1][0]$y$3518'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3525' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3526 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][3][0]$3527' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][3][0]$y$3528 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][3][0]$3529' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][3][0]$y$3530 = $memory\sq_figure$wrmux[9][2][0]$y$3524'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3531' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3532 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][4][0]$3533' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][4][0]$y$3534 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][4][0]$3535' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][4][0]$y$3536 = $memory\sq_figure$wrmux[9][3][0]$y$3530'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3537' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3538 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][5][0]$3539' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][5][0]$y$3540 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][5][0]$3541' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][5][0]$y$3542 = $memory\sq_figure$wrmux[9][4][0]$y$3536'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3543' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3544 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][6][0]$3545' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][6][0]$y$3546 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][6][0]$3547' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][6][0]$y$3548 = $memory\sq_figure$wrmux[9][5][0]$y$3542'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3549' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3550 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][7][0]$3551' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][7][0]$y$3552 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][7][0]$3553' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][7][0]$y$3554 = $memory\sq_figure$wrmux[9][6][0]$y$3548'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3555' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3556 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][8][0]$3557' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][8][0]$y$3558 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][8][0]$3559' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][8][0]$y$3560 = $memory\sq_figure$wrmux[9][7][0]$y$3554'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3561' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3562 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][9][0]$3563' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][9][0]$y$3564 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][9][0]$3565' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][9][0]$y$3566 = $memory\sq_figure$wrmux[9][8][0]$y$3560'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3567' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3568 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][10][0]$3569' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][10][0]$y$3570 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][10][0]$3571' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][10][0]$y$3572 = $memory\sq_figure$wrmux[9][9][0]$y$3566'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3573' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3574 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][11][0]$3575' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][11][0]$y$3576 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][11][0]$3577' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][11][0]$y$3578 = $memory\sq_figure$wrmux[9][10][0]$y$3572'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3579' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3580 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][12][0]$3581' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][12][0]$y$3582 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][12][0]$3583' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][12][0]$y$3584 = $memory\sq_figure$wrmux[9][11][0]$y$3578'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3585' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3586 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][13][0]$3587' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][13][0]$y$3588 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][13][0]$3589' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][13][0]$y$3590 = $memory\sq_figure$wrmux[9][12][0]$y$3584'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3591' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3592 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][14][0]$3593' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][14][0]$y$3594 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][14][0]$3595' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][14][0]$y$3596 = $memory\sq_figure$wrmux[9][13][0]$y$3590'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3597' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3598 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][15][0]$3599' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][15][0]$y$3600 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][15][0]$3601' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][15][0]$y$3602 = $memory\sq_figure$wrmux[9][14][0]$y$3596'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3603' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3604 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][16][0]$3605' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][16][0]$y$3606 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][16][0]$3607' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][16][0]$y$3608 = $memory\sq_figure$wrmux[9][15][0]$y$3602'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3609' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3610 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[9][17][0]$3611' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[9][17][0]$y$3612 = $auto$rtlil.cc:1698:Or$1369'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3615' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3616 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][18][0]$3617' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][18][0]$y$3618 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][18][0]$3619' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][18][0]$y$3620 = $memory\sq_figure$wrmux[9][17][0]$y$3614'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3621' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3622 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[9][19][0]$3623' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[9][19][0]$y$3624 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[9][19][0]$3625' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[9][19][0]$y$3626 = $memory\sq_figure$wrmux[9][18][0]$y$3620'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3627' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3628 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][0][0]$3629' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][0][0]$y$3630 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][0][0]$3631' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][0][0]$y$3632 = \sq_figure[10]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3633' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3634 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][1][0]$3635' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][1][0]$y$3636 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][1][0]$3637' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][1][0]$y$3638 = $memory\sq_figure$wrmux[10][0][0]$y$3632'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3639' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3640 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][2][0]$3641' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][2][0]$y$3642 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][2][0]$3643' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][2][0]$y$3644 = $memory\sq_figure$wrmux[10][1][0]$y$3638'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3645' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3646 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][3][0]$3647' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][3][0]$y$3648 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][3][0]$3649' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][3][0]$y$3650 = $memory\sq_figure$wrmux[10][2][0]$y$3644'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3651' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3652 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][4][0]$3653' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][4][0]$y$3654 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][4][0]$3655' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][4][0]$y$3656 = $memory\sq_figure$wrmux[10][3][0]$y$3650'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3657' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3658 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][5][0]$3659' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][5][0]$y$3660 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][5][0]$3661' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][5][0]$y$3662 = $memory\sq_figure$wrmux[10][4][0]$y$3656'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3663' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3664 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][6][0]$3665' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][6][0]$y$3666 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][6][0]$3667' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][6][0]$y$3668 = $memory\sq_figure$wrmux[10][5][0]$y$3662'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3669' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3670 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][7][0]$3671' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][7][0]$y$3672 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][7][0]$3673' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][7][0]$y$3674 = $memory\sq_figure$wrmux[10][6][0]$y$3668'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3675' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3676 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][8][0]$3677' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][8][0]$y$3678 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][8][0]$3679' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][8][0]$y$3680 = $memory\sq_figure$wrmux[10][7][0]$y$3674'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3681' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3682 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][9][0]$3683' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][9][0]$y$3684 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][9][0]$3685' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][9][0]$y$3686 = $memory\sq_figure$wrmux[10][8][0]$y$3680'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3687' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3688 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][10][0]$3689' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][10][0]$y$3690 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][10][0]$3691' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][10][0]$y$3692 = $memory\sq_figure$wrmux[10][9][0]$y$3686'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3693' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3694 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][11][0]$3695' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][11][0]$y$3696 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][11][0]$3697' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][11][0]$y$3698 = $memory\sq_figure$wrmux[10][10][0]$y$3692'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3699' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3700 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][12][0]$3701' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][12][0]$y$3702 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][12][0]$3703' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][12][0]$y$3704 = $memory\sq_figure$wrmux[10][11][0]$y$3698'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3705' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3706 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][13][0]$3707' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][13][0]$y$3708 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][13][0]$3709' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][13][0]$y$3710 = $memory\sq_figure$wrmux[10][12][0]$y$3704'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3711' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3712 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][14][0]$3713' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][14][0]$y$3714 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][14][0]$3715' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][14][0]$y$3716 = $memory\sq_figure$wrmux[10][13][0]$y$3710'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3717' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3718 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][15][0]$3719' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][15][0]$y$3720 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][15][0]$3721' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][15][0]$y$3722 = $memory\sq_figure$wrmux[10][14][0]$y$3716'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3723' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3724 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][16][0]$3725' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][16][0]$y$3726 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][16][0]$3727' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][16][0]$y$3728 = $memory\sq_figure$wrmux[10][15][0]$y$3722'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3729' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3730 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][17][0]$3731' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][17][0]$y$3732 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][17][0]$3733' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][17][0]$y$3734 = $memory\sq_figure$wrmux[10][16][0]$y$3728'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3735' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3736 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[10][18][0]$3737' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[10][18][0]$y$3738 = $auto$rtlil.cc:1698:Or$1369'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3741' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3742 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[10][19][0]$3743' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[10][19][0]$y$3744 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[10][19][0]$3745' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[10][19][0]$y$3746 = $memory\sq_figure$wrmux[10][18][0]$y$3740'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3747' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3748 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][0][0]$3749' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][0][0]$y$3750 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][0][0]$3751' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][0][0]$y$3752 = \sq_figure[11]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3753' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3754 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][1][0]$3755' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][1][0]$y$3756 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][1][0]$3757' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][1][0]$y$3758 = $memory\sq_figure$wrmux[11][0][0]$y$3752'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3759' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3760 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][2][0]$3761' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][2][0]$y$3762 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][2][0]$3763' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][2][0]$y$3764 = $memory\sq_figure$wrmux[11][1][0]$y$3758'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3765' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3766 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][3][0]$3767' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][3][0]$y$3768 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][3][0]$3769' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][3][0]$y$3770 = $memory\sq_figure$wrmux[11][2][0]$y$3764'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3771' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3772 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][4][0]$3773' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][4][0]$y$3774 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][4][0]$3775' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][4][0]$y$3776 = $memory\sq_figure$wrmux[11][3][0]$y$3770'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3777' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3778 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][5][0]$3779' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][5][0]$y$3780 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][5][0]$3781' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][5][0]$y$3782 = $memory\sq_figure$wrmux[11][4][0]$y$3776'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3783' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3784 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][6][0]$3785' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][6][0]$y$3786 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][6][0]$3787' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][6][0]$y$3788 = $memory\sq_figure$wrmux[11][5][0]$y$3782'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3789' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3790 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][7][0]$3791' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][7][0]$y$3792 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][7][0]$3793' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][7][0]$y$3794 = $memory\sq_figure$wrmux[11][6][0]$y$3788'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3795' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3796 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][8][0]$3797' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][8][0]$y$3798 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][8][0]$3799' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][8][0]$y$3800 = $memory\sq_figure$wrmux[11][7][0]$y$3794'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3801' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3802 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][9][0]$3803' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][9][0]$y$3804 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][9][0]$3805' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][9][0]$y$3806 = $memory\sq_figure$wrmux[11][8][0]$y$3800'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3807' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3808 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][10][0]$3809' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][10][0]$y$3810 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][10][0]$3811' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][10][0]$y$3812 = $memory\sq_figure$wrmux[11][9][0]$y$3806'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3813' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3814 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][11][0]$3815' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][11][0]$y$3816 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][11][0]$3817' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][11][0]$y$3818 = $memory\sq_figure$wrmux[11][10][0]$y$3812'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3819' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3820 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][12][0]$3821' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][12][0]$y$3822 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][12][0]$3823' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][12][0]$y$3824 = $memory\sq_figure$wrmux[11][11][0]$y$3818'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3825' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3826 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][13][0]$3827' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][13][0]$y$3828 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][13][0]$3829' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][13][0]$y$3830 = $memory\sq_figure$wrmux[11][12][0]$y$3824'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3831' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3832 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][14][0]$3833' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][14][0]$y$3834 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][14][0]$3835' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][14][0]$y$3836 = $memory\sq_figure$wrmux[11][13][0]$y$3830'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3837' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3838 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][15][0]$3839' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][15][0]$y$3840 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][15][0]$3841' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][15][0]$y$3842 = $memory\sq_figure$wrmux[11][14][0]$y$3836'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3843' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3844 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][16][0]$3845' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][16][0]$y$3846 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][16][0]$3847' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][16][0]$y$3848 = $memory\sq_figure$wrmux[11][15][0]$y$3842'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3849' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3850 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][17][0]$3851' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][17][0]$y$3852 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][17][0]$3853' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][17][0]$y$3854 = $memory\sq_figure$wrmux[11][16][0]$y$3848'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3855' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3856 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[11][18][0]$3857' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[11][18][0]$y$3858 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[11][18][0]$3859' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[11][18][0]$y$3860 = $memory\sq_figure$wrmux[11][17][0]$y$3854'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3861' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3862 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[11][19][0]$3863' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[11][19][0]$y$3864 = $auto$rtlil.cc:1698:Or$1369'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3867' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3868 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3869' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3870 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][0][0]$3871' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][0][0]$y$3872 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][0][0]$3873' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][0][0]$y$3874 = \sq_figure[12]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3875' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3876 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][1][0]$3877' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][1][0]$y$3878 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][1][0]$3879' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][1][0]$y$3880 = $memory\sq_figure$wrmux[12][0][0]$y$3874'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3881' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3882 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][2][0]$3883' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][2][0]$y$3884 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][2][0]$3885' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][2][0]$y$3886 = $memory\sq_figure$wrmux[12][1][0]$y$3880'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3887' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3888 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][3][0]$3889' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][3][0]$y$3890 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][3][0]$3891' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][3][0]$y$3892 = $memory\sq_figure$wrmux[12][2][0]$y$3886'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3893' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3894 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3895' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3896 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][4][0]$3897' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][4][0]$y$3898 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][4][0]$3899' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][4][0]$y$3900 = $memory\sq_figure$wrmux[12][3][0]$y$3892'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3901' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3902 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][5][0]$3903' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][5][0]$y$3904 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][5][0]$3905' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][5][0]$y$3906 = $memory\sq_figure$wrmux[12][4][0]$y$3900'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3907' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3908 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][6][0]$3909' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][6][0]$y$3910 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][6][0]$3911' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][6][0]$y$3912 = $memory\sq_figure$wrmux[12][5][0]$y$3906'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3913' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3914 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][7][0]$3915' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][7][0]$y$3916 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][7][0]$3917' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][7][0]$y$3918 = $memory\sq_figure$wrmux[12][6][0]$y$3912'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3919' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3920 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3921' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3922 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[12][8][0]$3923' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[12][8][0]$y$3924 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3927' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3928 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][9][0]$3929' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][9][0]$y$3930 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][9][0]$3931' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][9][0]$y$3932 = $memory\sq_figure$wrmux[12][8][0]$y$3926'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3933' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3934 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][10][0]$3935' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][10][0]$y$3936 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][10][0]$3937' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][10][0]$y$3938 = $memory\sq_figure$wrmux[12][9][0]$y$3932'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3939' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3940 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][11][0]$3941' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][11][0]$y$3942 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][11][0]$3943' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][11][0]$y$3944 = $memory\sq_figure$wrmux[12][10][0]$y$3938'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3945' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3946 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3947' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3948 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][12][0]$3949' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][12][0]$y$3950 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][12][0]$3951' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][12][0]$y$3952 = $memory\sq_figure$wrmux[12][11][0]$y$3944'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3953' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3954 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][13][0]$3955' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][13][0]$y$3956 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][13][0]$3957' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][13][0]$y$3958 = $memory\sq_figure$wrmux[12][12][0]$y$3952'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3959' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3960 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][14][0]$3961' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][14][0]$y$3962 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][14][0]$3963' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][14][0]$y$3964 = $memory\sq_figure$wrmux[12][13][0]$y$3958'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3965' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3966 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][15][0]$3967' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][15][0]$y$3968 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][15][0]$3969' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][15][0]$y$3970 = $memory\sq_figure$wrmux[12][14][0]$y$3964'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3971' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3972 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3973' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3974 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][16][0]$3975' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][16][0]$y$3976 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][16][0]$3977' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][16][0]$y$3978 = $memory\sq_figure$wrmux[12][15][0]$y$3970'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3979' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3980 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][17][0]$3981' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][17][0]$y$3982 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][17][0]$3983' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][17][0]$y$3984 = $memory\sq_figure$wrmux[12][16][0]$y$3978'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3985' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3986 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][18][0]$3987' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][18][0]$y$3988 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][18][0]$3989' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][18][0]$y$3990 = $memory\sq_figure$wrmux[12][17][0]$y$3984'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3991' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3992 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[12][19][0]$3993' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[12][19][0]$y$3994 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[12][19][0]$3995' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[12][19][0]$y$3996 = $memory\sq_figure$wrmux[12][18][0]$y$3990'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$3997' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$3998 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][0][0]$3999' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][0][0]$y$4000 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][0][0]$4001' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][0][0]$y$4002 = \sq_figure[13]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4003' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4004 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][1][0]$4005' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][1][0]$y$4006 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][1][0]$4007' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][1][0]$y$4008 = $memory\sq_figure$wrmux[13][0][0]$y$4002'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4009' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4010 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][2][0]$4011' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][2][0]$y$4012 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][2][0]$4013' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][2][0]$y$4014 = $memory\sq_figure$wrmux[13][1][0]$y$4008'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4015' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4016 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][3][0]$4017' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][3][0]$y$4018 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][3][0]$4019' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][3][0]$y$4020 = $memory\sq_figure$wrmux[13][2][0]$y$4014'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4021' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4022 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][4][0]$4023' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][4][0]$y$4024 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][4][0]$4025' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][4][0]$y$4026 = $memory\sq_figure$wrmux[13][3][0]$y$4020'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4027' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4028 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][5][0]$4029' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][5][0]$y$4030 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][5][0]$4031' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][5][0]$y$4032 = $memory\sq_figure$wrmux[13][4][0]$y$4026'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4033' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4034 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][6][0]$4035' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][6][0]$y$4036 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][6][0]$4037' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][6][0]$y$4038 = $memory\sq_figure$wrmux[13][5][0]$y$4032'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4039' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4040 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][7][0]$4041' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][7][0]$y$4042 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][7][0]$4043' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][7][0]$y$4044 = $memory\sq_figure$wrmux[13][6][0]$y$4038'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4045' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4046 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][8][0]$4047' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][8][0]$y$4048 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][8][0]$4049' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][8][0]$y$4050 = $memory\sq_figure$wrmux[13][7][0]$y$4044'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4051' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4052 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[13][9][0]$4053' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[13][9][0]$y$4054 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4057' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4058 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][10][0]$4059' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][10][0]$y$4060 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][10][0]$4061' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][10][0]$y$4062 = $memory\sq_figure$wrmux[13][9][0]$y$4056'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4063' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4064 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][11][0]$4065' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][11][0]$y$4066 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][11][0]$4067' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][11][0]$y$4068 = $memory\sq_figure$wrmux[13][10][0]$y$4062'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4069' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4070 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][12][0]$4071' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][12][0]$y$4072 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][12][0]$4073' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][12][0]$y$4074 = $memory\sq_figure$wrmux[13][11][0]$y$4068'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4075' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4076 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][13][0]$4077' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][13][0]$y$4078 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][13][0]$4079' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][13][0]$y$4080 = $memory\sq_figure$wrmux[13][12][0]$y$4074'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4081' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4082 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][14][0]$4083' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][14][0]$y$4084 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][14][0]$4085' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][14][0]$y$4086 = $memory\sq_figure$wrmux[13][13][0]$y$4080'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4087' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4088 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][15][0]$4089' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][15][0]$y$4090 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][15][0]$4091' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][15][0]$y$4092 = $memory\sq_figure$wrmux[13][14][0]$y$4086'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4093' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4094 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][16][0]$4095' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][16][0]$y$4096 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][16][0]$4097' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][16][0]$y$4098 = $memory\sq_figure$wrmux[13][15][0]$y$4092'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4099' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4100 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][17][0]$4101' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][17][0]$y$4102 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][17][0]$4103' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][17][0]$y$4104 = $memory\sq_figure$wrmux[13][16][0]$y$4098'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4105' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4106 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][18][0]$4107' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][18][0]$y$4108 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][18][0]$4109' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][18][0]$y$4110 = $memory\sq_figure$wrmux[13][17][0]$y$4104'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4111' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4112 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[13][19][0]$4113' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[13][19][0]$y$4114 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[13][19][0]$4115' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[13][19][0]$y$4116 = $memory\sq_figure$wrmux[13][18][0]$y$4110'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4117' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4118 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][0][0]$4119' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][0][0]$y$4120 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][0][0]$4121' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][0][0]$y$4122 = \sq_figure[14]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4123' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4124 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][1][0]$4125' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][1][0]$y$4126 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][1][0]$4127' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][1][0]$y$4128 = $memory\sq_figure$wrmux[14][0][0]$y$4122'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4129' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4130 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][2][0]$4131' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][2][0]$y$4132 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][2][0]$4133' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][2][0]$y$4134 = $memory\sq_figure$wrmux[14][1][0]$y$4128'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4135' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4136 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][3][0]$4137' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][3][0]$y$4138 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][3][0]$4139' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][3][0]$y$4140 = $memory\sq_figure$wrmux[14][2][0]$y$4134'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4141' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4142 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][4][0]$4143' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][4][0]$y$4144 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][4][0]$4145' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][4][0]$y$4146 = $memory\sq_figure$wrmux[14][3][0]$y$4140'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4147' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4148 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][5][0]$4149' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][5][0]$y$4150 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][5][0]$4151' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][5][0]$y$4152 = $memory\sq_figure$wrmux[14][4][0]$y$4146'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4153' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4154 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][6][0]$4155' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][6][0]$y$4156 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][6][0]$4157' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][6][0]$y$4158 = $memory\sq_figure$wrmux[14][5][0]$y$4152'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4159' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4160 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][7][0]$4161' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][7][0]$y$4162 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][7][0]$4163' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][7][0]$y$4164 = $memory\sq_figure$wrmux[14][6][0]$y$4158'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4165' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4166 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][8][0]$4167' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][8][0]$y$4168 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][8][0]$4169' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][8][0]$y$4170 = $memory\sq_figure$wrmux[14][7][0]$y$4164'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4171' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4172 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][9][0]$4173' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][9][0]$y$4174 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][9][0]$4175' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][9][0]$y$4176 = $memory\sq_figure$wrmux[14][8][0]$y$4170'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4177' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4178 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[14][10][0]$4179' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[14][10][0]$y$4180 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4183' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4184 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][11][0]$4185' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][11][0]$y$4186 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][11][0]$4187' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][11][0]$y$4188 = $memory\sq_figure$wrmux[14][10][0]$y$4182'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4189' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4190 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][12][0]$4191' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][12][0]$y$4192 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][12][0]$4193' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][12][0]$y$4194 = $memory\sq_figure$wrmux[14][11][0]$y$4188'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4195' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4196 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][13][0]$4197' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][13][0]$y$4198 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][13][0]$4199' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][13][0]$y$4200 = $memory\sq_figure$wrmux[14][12][0]$y$4194'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4201' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4202 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][14][0]$4203' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][14][0]$y$4204 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][14][0]$4205' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][14][0]$y$4206 = $memory\sq_figure$wrmux[14][13][0]$y$4200'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4207' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4208 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][15][0]$4209' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][15][0]$y$4210 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][15][0]$4211' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][15][0]$y$4212 = $memory\sq_figure$wrmux[14][14][0]$y$4206'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4213' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4214 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][16][0]$4215' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][16][0]$y$4216 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][16][0]$4217' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][16][0]$y$4218 = $memory\sq_figure$wrmux[14][15][0]$y$4212'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4219' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4220 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][17][0]$4221' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][17][0]$y$4222 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][17][0]$4223' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][17][0]$y$4224 = $memory\sq_figure$wrmux[14][16][0]$y$4218'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4225' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4226 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][18][0]$4227' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][18][0]$y$4228 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][18][0]$4229' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][18][0]$y$4230 = $memory\sq_figure$wrmux[14][17][0]$y$4224'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4231' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4232 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[14][19][0]$4233' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[14][19][0]$y$4234 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[14][19][0]$4235' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[14][19][0]$y$4236 = $memory\sq_figure$wrmux[14][18][0]$y$4230'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4237' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4238 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][0][0]$4239' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][0][0]$y$4240 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][0][0]$4241' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][0][0]$y$4242 = \sq_figure[15]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4243' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4244 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][1][0]$4245' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][1][0]$y$4246 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][1][0]$4247' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][1][0]$y$4248 = $memory\sq_figure$wrmux[15][0][0]$y$4242'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4249' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4250 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][2][0]$4251' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][2][0]$y$4252 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][2][0]$4253' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][2][0]$y$4254 = $memory\sq_figure$wrmux[15][1][0]$y$4248'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4255' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4256 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][3][0]$4257' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][3][0]$y$4258 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][3][0]$4259' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][3][0]$y$4260 = $memory\sq_figure$wrmux[15][2][0]$y$4254'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4261' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4262 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][4][0]$4263' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][4][0]$y$4264 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][4][0]$4265' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][4][0]$y$4266 = $memory\sq_figure$wrmux[15][3][0]$y$4260'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4267' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4268 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][5][0]$4269' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][5][0]$y$4270 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][5][0]$4271' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][5][0]$y$4272 = $memory\sq_figure$wrmux[15][4][0]$y$4266'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4273' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4274 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][6][0]$4275' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][6][0]$y$4276 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][6][0]$4277' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][6][0]$y$4278 = $memory\sq_figure$wrmux[15][5][0]$y$4272'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4279' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4280 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][7][0]$4281' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][7][0]$y$4282 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][7][0]$4283' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][7][0]$y$4284 = $memory\sq_figure$wrmux[15][6][0]$y$4278'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4285' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4286 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][8][0]$4287' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][8][0]$y$4288 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][8][0]$4289' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][8][0]$y$4290 = $memory\sq_figure$wrmux[15][7][0]$y$4284'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4291' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4292 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][9][0]$4293' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][9][0]$y$4294 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][9][0]$4295' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][9][0]$y$4296 = $memory\sq_figure$wrmux[15][8][0]$y$4290'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4297' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4298 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][10][0]$4299' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][10][0]$y$4300 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][10][0]$4301' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][10][0]$y$4302 = $memory\sq_figure$wrmux[15][9][0]$y$4296'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4303' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4304 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[15][11][0]$4305' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[15][11][0]$y$4306 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4309' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4310 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][12][0]$4311' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][12][0]$y$4312 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][12][0]$4313' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][12][0]$y$4314 = $memory\sq_figure$wrmux[15][11][0]$y$4308'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4315' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4316 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][13][0]$4317' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][13][0]$y$4318 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][13][0]$4319' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][13][0]$y$4320 = $memory\sq_figure$wrmux[15][12][0]$y$4314'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4321' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4322 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][14][0]$4323' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][14][0]$y$4324 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][14][0]$4325' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][14][0]$y$4326 = $memory\sq_figure$wrmux[15][13][0]$y$4320'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4327' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4328 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][15][0]$4329' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][15][0]$y$4330 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][15][0]$4331' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][15][0]$y$4332 = $memory\sq_figure$wrmux[15][14][0]$y$4326'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4333' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4334 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][16][0]$4335' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][16][0]$y$4336 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][16][0]$4337' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][16][0]$y$4338 = $memory\sq_figure$wrmux[15][15][0]$y$4332'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4339' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4340 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][17][0]$4341' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][17][0]$y$4342 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][17][0]$4343' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][17][0]$y$4344 = $memory\sq_figure$wrmux[15][16][0]$y$4338'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4345' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4346 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][18][0]$4347' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][18][0]$y$4348 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][18][0]$4349' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][18][0]$y$4350 = $memory\sq_figure$wrmux[15][17][0]$y$4344'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4351' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4352 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[15][19][0]$4353' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[15][19][0]$y$4354 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[15][19][0]$4355' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[15][19][0]$y$4356 = $memory\sq_figure$wrmux[15][18][0]$y$4350'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4357' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4358 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4359' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4360 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][0][0]$4361' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][0][0]$y$4362 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][0][0]$4363' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][0][0]$y$4364 = \sq_figure[16]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4365' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4366 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][1][0]$4367' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][1][0]$y$4368 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][1][0]$4369' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][1][0]$y$4370 = $memory\sq_figure$wrmux[16][0][0]$y$4364'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4371' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4372 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][2][0]$4373' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][2][0]$y$4374 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][2][0]$4375' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][2][0]$y$4376 = $memory\sq_figure$wrmux[16][1][0]$y$4370'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4377' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4378 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][3][0]$4379' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][3][0]$y$4380 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][3][0]$4381' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][3][0]$y$4382 = $memory\sq_figure$wrmux[16][2][0]$y$4376'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4383' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4384 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4385' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4386 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][4][0]$4387' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][4][0]$y$4388 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][4][0]$4389' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][4][0]$y$4390 = $memory\sq_figure$wrmux[16][3][0]$y$4382'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4391' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4392 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][5][0]$4393' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][5][0]$y$4394 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][5][0]$4395' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][5][0]$y$4396 = $memory\sq_figure$wrmux[16][4][0]$y$4390'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4397' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4398 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][6][0]$4399' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][6][0]$y$4400 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][6][0]$4401' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][6][0]$y$4402 = $memory\sq_figure$wrmux[16][5][0]$y$4396'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4403' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4404 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][7][0]$4405' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][7][0]$y$4406 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][7][0]$4407' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][7][0]$y$4408 = $memory\sq_figure$wrmux[16][6][0]$y$4402'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4409' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4410 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4411' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4412 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][8][0]$4413' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][8][0]$y$4414 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][8][0]$4415' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][8][0]$y$4416 = $memory\sq_figure$wrmux[16][7][0]$y$4408'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4417' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4418 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][9][0]$4419' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][9][0]$y$4420 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][9][0]$4421' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][9][0]$y$4422 = $memory\sq_figure$wrmux[16][8][0]$y$4416'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4423' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4424 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][10][0]$4425' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][10][0]$y$4426 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][10][0]$4427' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][10][0]$y$4428 = $memory\sq_figure$wrmux[16][9][0]$y$4422'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4429' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4430 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][11][0]$4431' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][11][0]$y$4432 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][11][0]$4433' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][11][0]$y$4434 = $memory\sq_figure$wrmux[16][10][0]$y$4428'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4435' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4436 = 1'1'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4437' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4438 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[16][12][0]$4439' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[16][12][0]$y$4440 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4443' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4444 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][13][0]$4445' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][13][0]$y$4446 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][13][0]$4447' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][13][0]$y$4448 = $memory\sq_figure$wrmux[16][12][0]$y$4442'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4449' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4450 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][14][0]$4451' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][14][0]$y$4452 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][14][0]$4453' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][14][0]$y$4454 = $memory\sq_figure$wrmux[16][13][0]$y$4448'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4455' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4456 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][15][0]$4457' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][15][0]$y$4458 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][15][0]$4459' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][15][0]$y$4460 = $memory\sq_figure$wrmux[16][14][0]$y$4454'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4461' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4462 = 1'0'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4463' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4464 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][16][0]$4465' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][16][0]$y$4466 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][16][0]$4467' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][16][0]$y$4468 = $memory\sq_figure$wrmux[16][15][0]$y$4460'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4469' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4470 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][17][0]$4471' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][17][0]$y$4472 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][17][0]$4473' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][17][0]$y$4474 = $memory\sq_figure$wrmux[16][16][0]$y$4468'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4475' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4476 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][18][0]$4477' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][18][0]$y$4478 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][18][0]$4479' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][18][0]$y$4480 = $memory\sq_figure$wrmux[16][17][0]$y$4474'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4481' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4482 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[16][19][0]$4483' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[16][19][0]$y$4484 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[16][19][0]$4485' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[16][19][0]$y$4486 = $memory\sq_figure$wrmux[16][18][0]$y$4480'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4487' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4488 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][0][0]$4489' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][0][0]$y$4490 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][0][0]$4491' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][0][0]$y$4492 = \sq_figure[17]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4493' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4494 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][1][0]$4495' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][1][0]$y$4496 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][1][0]$4497' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][1][0]$y$4498 = $memory\sq_figure$wrmux[17][0][0]$y$4492'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4499' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4500 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][2][0]$4501' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][2][0]$y$4502 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][2][0]$4503' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][2][0]$y$4504 = $memory\sq_figure$wrmux[17][1][0]$y$4498'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4505' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4506 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][3][0]$4507' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][3][0]$y$4508 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][3][0]$4509' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][3][0]$y$4510 = $memory\sq_figure$wrmux[17][2][0]$y$4504'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4511' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4512 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][4][0]$4513' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][4][0]$y$4514 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][4][0]$4515' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][4][0]$y$4516 = $memory\sq_figure$wrmux[17][3][0]$y$4510'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4517' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4518 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][5][0]$4519' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][5][0]$y$4520 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][5][0]$4521' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][5][0]$y$4522 = $memory\sq_figure$wrmux[17][4][0]$y$4516'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4523' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4524 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][6][0]$4525' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][6][0]$y$4526 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][6][0]$4527' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][6][0]$y$4528 = $memory\sq_figure$wrmux[17][5][0]$y$4522'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4529' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4530 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][7][0]$4531' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][7][0]$y$4532 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][7][0]$4533' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][7][0]$y$4534 = $memory\sq_figure$wrmux[17][6][0]$y$4528'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4535' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4536 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][8][0]$4537' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][8][0]$y$4538 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][8][0]$4539' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][8][0]$y$4540 = $memory\sq_figure$wrmux[17][7][0]$y$4534'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4541' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4542 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][9][0]$4543' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][9][0]$y$4544 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][9][0]$4545' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][9][0]$y$4546 = $memory\sq_figure$wrmux[17][8][0]$y$4540'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4547' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4548 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][10][0]$4549' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][10][0]$y$4550 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][10][0]$4551' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][10][0]$y$4552 = $memory\sq_figure$wrmux[17][9][0]$y$4546'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4553' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4554 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][11][0]$4555' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][11][0]$y$4556 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][11][0]$4557' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][11][0]$y$4558 = $memory\sq_figure$wrmux[17][10][0]$y$4552'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4559' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4560 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][12][0]$4561' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][12][0]$y$4562 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][12][0]$4563' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][12][0]$y$4564 = $memory\sq_figure$wrmux[17][11][0]$y$4558'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4565' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4566 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[17][13][0]$4567' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[17][13][0]$y$4568 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4571' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4572 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][14][0]$4573' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][14][0]$y$4574 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][14][0]$4575' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][14][0]$y$4576 = $memory\sq_figure$wrmux[17][13][0]$y$4570'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4577' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4578 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][15][0]$4579' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][15][0]$y$4580 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][15][0]$4581' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][15][0]$y$4582 = $memory\sq_figure$wrmux[17][14][0]$y$4576'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4583' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4584 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][16][0]$4585' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][16][0]$y$4586 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][16][0]$4587' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][16][0]$y$4588 = $memory\sq_figure$wrmux[17][15][0]$y$4582'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4589' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4590 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][17][0]$4591' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][17][0]$y$4592 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][17][0]$4593' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][17][0]$y$4594 = $memory\sq_figure$wrmux[17][16][0]$y$4588'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4595' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4596 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][18][0]$4597' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][18][0]$y$4598 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][18][0]$4599' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][18][0]$y$4600 = $memory\sq_figure$wrmux[17][17][0]$y$4594'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4601' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4602 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[17][19][0]$4603' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[17][19][0]$y$4604 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[17][19][0]$4605' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[17][19][0]$y$4606 = $memory\sq_figure$wrmux[17][18][0]$y$4600'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4607' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4608 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][0][0]$4609' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][0][0]$y$4610 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][0][0]$4611' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][0][0]$y$4612 = \sq_figure[18]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4613' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4614 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][1][0]$4615' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][1][0]$y$4616 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][1][0]$4617' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][1][0]$y$4618 = $memory\sq_figure$wrmux[18][0][0]$y$4612'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4619' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4620 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][2][0]$4621' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][2][0]$y$4622 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][2][0]$4623' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][2][0]$y$4624 = $memory\sq_figure$wrmux[18][1][0]$y$4618'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4625' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4626 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][3][0]$4627' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][3][0]$y$4628 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][3][0]$4629' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][3][0]$y$4630 = $memory\sq_figure$wrmux[18][2][0]$y$4624'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4631' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4632 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][4][0]$4633' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][4][0]$y$4634 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][4][0]$4635' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][4][0]$y$4636 = $memory\sq_figure$wrmux[18][3][0]$y$4630'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4637' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4638 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][5][0]$4639' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][5][0]$y$4640 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][5][0]$4641' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][5][0]$y$4642 = $memory\sq_figure$wrmux[18][4][0]$y$4636'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4643' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4644 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][6][0]$4645' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][6][0]$y$4646 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][6][0]$4647' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][6][0]$y$4648 = $memory\sq_figure$wrmux[18][5][0]$y$4642'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4649' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4650 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][7][0]$4651' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][7][0]$y$4652 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][7][0]$4653' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][7][0]$y$4654 = $memory\sq_figure$wrmux[18][6][0]$y$4648'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4655' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4656 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][8][0]$4657' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][8][0]$y$4658 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][8][0]$4659' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][8][0]$y$4660 = $memory\sq_figure$wrmux[18][7][0]$y$4654'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4661' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4662 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][9][0]$4663' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][9][0]$y$4664 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][9][0]$4665' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][9][0]$y$4666 = $memory\sq_figure$wrmux[18][8][0]$y$4660'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4667' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4668 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][10][0]$4669' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][10][0]$y$4670 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][10][0]$4671' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][10][0]$y$4672 = $memory\sq_figure$wrmux[18][9][0]$y$4666'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4673' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4674 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][11][0]$4675' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][11][0]$y$4676 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][11][0]$4677' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][11][0]$y$4678 = $memory\sq_figure$wrmux[18][10][0]$y$4672'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4679' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4680 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][12][0]$4681' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][12][0]$y$4682 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][12][0]$4683' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][12][0]$y$4684 = $memory\sq_figure$wrmux[18][11][0]$y$4678'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4685' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4686 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][13][0]$4687' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][13][0]$y$4688 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][13][0]$4689' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][13][0]$y$4690 = $memory\sq_figure$wrmux[18][12][0]$y$4684'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4691' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4692 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[18][14][0]$4693' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[18][14][0]$y$4694 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4697' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4698 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][15][0]$4699' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][15][0]$y$4700 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][15][0]$4701' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][15][0]$y$4702 = $memory\sq_figure$wrmux[18][14][0]$y$4696'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4703' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4704 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][16][0]$4705' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][16][0]$y$4706 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][16][0]$4707' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][16][0]$y$4708 = $memory\sq_figure$wrmux[18][15][0]$y$4702'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4709' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4710 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][17][0]$4711' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][17][0]$y$4712 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][17][0]$4713' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][17][0]$y$4714 = $memory\sq_figure$wrmux[18][16][0]$y$4708'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4715' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4716 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][18][0]$4717' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][18][0]$y$4718 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][18][0]$4719' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][18][0]$y$4720 = $memory\sq_figure$wrmux[18][17][0]$y$4714'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4721' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4722 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[18][19][0]$4723' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[18][19][0]$y$4724 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[18][19][0]$4725' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[18][19][0]$y$4726 = $memory\sq_figure$wrmux[18][18][0]$y$4720'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4727' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4728 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][0][0]$4729' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][0][0]$y$4730 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][0][0]$4731' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][0][0]$y$4732 = \sq_figure[19]'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4733' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4734 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][1][0]$4735' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][1][0]$y$4736 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][1][0]$4737' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][1][0]$y$4738 = $memory\sq_figure$wrmux[19][0][0]$y$4732'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4739' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4740 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][2][0]$4741' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][2][0]$y$4742 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][2][0]$4743' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][2][0]$y$4744 = $memory\sq_figure$wrmux[19][1][0]$y$4738'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4745' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4746 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][3][0]$4747' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][3][0]$y$4748 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][3][0]$4749' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][3][0]$y$4750 = $memory\sq_figure$wrmux[19][2][0]$y$4744'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4751' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4752 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][4][0]$4753' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][4][0]$y$4754 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][4][0]$4755' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][4][0]$y$4756 = $memory\sq_figure$wrmux[19][3][0]$y$4750'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4757' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4758 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][5][0]$4759' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][5][0]$y$4760 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][5][0]$4761' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][5][0]$y$4762 = $memory\sq_figure$wrmux[19][4][0]$y$4756'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4763' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4764 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][6][0]$4765' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][6][0]$y$4766 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][6][0]$4767' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][6][0]$y$4768 = $memory\sq_figure$wrmux[19][5][0]$y$4762'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4769' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4770 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][7][0]$4771' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][7][0]$y$4772 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][7][0]$4773' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][7][0]$y$4774 = $memory\sq_figure$wrmux[19][6][0]$y$4768'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4775' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4776 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][8][0]$4777' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][8][0]$y$4778 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][8][0]$4779' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][8][0]$y$4780 = $memory\sq_figure$wrmux[19][7][0]$y$4774'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4781' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4782 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][9][0]$4783' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][9][0]$y$4784 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][9][0]$4785' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][9][0]$y$4786 = $memory\sq_figure$wrmux[19][8][0]$y$4780'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4787' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4788 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][10][0]$4789' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][10][0]$y$4790 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][10][0]$4791' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][10][0]$y$4792 = $memory\sq_figure$wrmux[19][9][0]$y$4786'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4793' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4794 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][11][0]$4795' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][11][0]$y$4796 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][11][0]$4797' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][11][0]$y$4798 = $memory\sq_figure$wrmux[19][10][0]$y$4792'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4799' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4800 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][12][0]$4801' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][12][0]$y$4802 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][12][0]$4803' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][12][0]$y$4804 = $memory\sq_figure$wrmux[19][11][0]$y$4798'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4805' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4806 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][13][0]$4807' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][13][0]$y$4808 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][13][0]$4809' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][13][0]$y$4810 = $memory\sq_figure$wrmux[19][12][0]$y$4804'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4811' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4812 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][14][0]$4813' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][14][0]$y$4814 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][14][0]$4815' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][14][0]$y$4816 = $memory\sq_figure$wrmux[19][13][0]$y$4810'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4817' (1'1, 1'1) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4818 = 1'1'. Replacing $and cell `$memory\sq_figure$wren[19][15][0]$4819' (and_or_buffer) in module `\top' with constant driver `$memory\sq_figure$wren[19][15][0]$y$4820 = \reset'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4823' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4824 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][16][0]$4825' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][16][0]$y$4826 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][16][0]$4827' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][16][0]$y$4828 = $memory\sq_figure$wrmux[19][15][0]$y$4822'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4829' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4830 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][17][0]$4831' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][17][0]$y$4832 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][17][0]$4833' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][17][0]$y$4834 = $memory\sq_figure$wrmux[19][16][0]$y$4828'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4835' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4836 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][18][0]$4837' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][18][0]$y$4838 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][18][0]$4839' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][18][0]$y$4840 = $memory\sq_figure$wrmux[19][17][0]$y$4834'. Replacing $and cell `$auto$memory_map.cc:70:addr_decode$4841' (const_and) in module `\top' with constant driver `$auto$rtlil.cc:1697:And$4842 = 1'0'. Replacing $and cell `$memory\sq_figure$wren[19][19][0]$4843' (const_and) in module `\top' with constant driver `$memory\sq_figure$wren[19][19][0]$y$4844 = 1'0'. Replacing $mux cell `$memory\sq_figure$wrmux[19][19][0]$4845' (0) in module `\top' with constant driver `$memory\sq_figure$wrmux[19][19][0]$y$4846 = $memory\sq_figure$wrmux[19][18][0]$y$4840'. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $memory\sq_figure$wrmux[13][9][0]$4055 (pure) Root of a mux tree: $memory\sq_figure$wrmux[4][4][0]$2919 (pure) Root of a mux tree: $memory\sq_figure$wrmux[3][3][0]$2789 (pure) Root of a mux tree: $memory\sq_figure$wrmux[11][19][0]$3865 (pure) Root of a mux tree: $memory\sq_figure$wrmux[17][13][0]$4569 (pure) Root of a mux tree: $memory\sq_figure$wrmux[5][5][0]$3051 (pure) Root of a mux tree: $memory\sq_figure$wrmux[16][12][0]$4441 (pure) Root of a mux tree: $memory\sq_figure$wrmux[8][16][0]$3487 (pure) Root of a mux tree: $memory\sq_figure$wrmux[2][2][0]$2653 (pure) Root of a mux tree: $memory\sq_figure$wrmux[7][7][0]$3303 (pure) Root of a mux tree: $memory\sq_figure$wrmux[19][15][0]$4821 (pure) Root of a mux tree: $memory\sq_figure$wrmux[15][11][0]$4307 (pure) Root of a mux tree: $memory\sq_figure$wrmux[18][14][0]$4695 (pure) Root of a mux tree: $memory\sq_figure$wrmux[14][10][0]$4181 (pure) Root of a mux tree: $memory\sq_figure$wrmux[1][1][0]$2517 (pure) Root of a mux tree: $memory\sq_figure$wrmux[12][8][0]$3925 (pure) Root of a mux tree: $memory\sq_figure$wrmux[9][17][0]$3613 (pure) Root of a mux tree: $memory\sq_figure$wrmux[10][18][0]$3739 (pure) Root of a mux tree: $memory\sq_figure$wrmux[0][0][0]$2367 (pure) Root of a mux tree: $memory\sq_figure$rdmux[0][0][0]$1892 (pure) Root of a mux tree: $procmux$229 Root of a mux tree: $procmux$247 (pure) Root of a mux tree: $procmux$262 Root of a mux tree: $procmux$280 (pure) Root of a mux tree: $procmux$289 Root of a mux tree: $procmux$307 (pure) Root of a mux tree: $procmux$313 Root of a mux tree: $procmux$331 (pure) Root of a mux tree: $procmux$337 Root of a mux tree: $procmux$355 (pure) Root of a mux tree: $procmux$361 Root of a mux tree: $procmux$379 (pure) Root of a mux tree: $procmux$385 Root of a mux tree: $procmux$403 (pure) Root of a mux tree: $procmux$409 Root of a mux tree: $procmux$427 (pure) Root of a mux tree: $procmux$659 Root of a mux tree: $procmux$667 Root of a mux tree: $procmux$680 Root of a mux tree: $procmux$695 (pure) Root of a mux tree: $procmux$702 Root of a mux tree: $procmux$710 Root of a mux tree: $procmux$717 Root of a mux tree: $procmux$728 Root of a mux tree: $procmux$738 (pure) Removing pure flag from root mux $procmux$702. Root of a mux tree: $procmux$745 Root of a mux tree: $procmux$753 Root of a mux tree: $procmux$766 Root of a mux tree: $procmux$781 (pure) Root of a mux tree: $procmux$788 Root of a mux tree: $procmux$796 Root of a mux tree: $procmux$803 Root of a mux tree: $procmux$814 Root of a mux tree: $procmux$824 (pure) Removing pure flag from root mux $procmux$788. Root of a mux tree: $procmux$827 (pure) Root of a mux tree: $procmux$839 (pure) Root of a mux tree: $procmux$854 (pure) Root of a mux tree: $procmux$857 Root of a mux tree: $procmux$864 Root of a mux tree: $procmux$872 (pure) Root of a mux tree: $procmux$875 Root of a mux tree: $procmux$882 Root of a mux tree: $procmux$890 (pure) Root of a mux tree: $procmux$905 (pure) Root of a mux tree: $procmux$911 (pure) Root of a mux tree: $procmux$917 (pure) Root of a mux tree: $procmux$923 (pure) Root of a mux tree: $procmux$929 (pure) Root of a mux tree: $procmux$935 (pure) Root of a mux tree: $procmux$948 Root of a mux tree: $procmux$953 (pure) Root of a mux tree: $procmux$973 (pure) Root of a mux tree: $memory\sq_figure$wrmux[6][6][0]$3177 (pure) Root of a mux tree: $procmux$788 (rerun as non-pure) Root of a mux tree: $procmux$702 (rerun as non-pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$946: Old ports: A=3'000, B=3'111, Y=$procmux$946_Y New ports: A=1'0, B=1'1, Y=$procmux$946_Y [0] New connections: $procmux$946_Y [2:1] = { $procmux$946_Y [0] $procmux$946_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$948: Old ports: A=3'000, B=$procmux$946_Y, Y=$procmux$948_Y New ports: A=1'0, B=$procmux$946_Y [0], Y=$procmux$948_Y [0] New connections: $procmux$948_Y [2:1] = { $procmux$948_Y [0] $procmux$948_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$951: Old ports: A=$procmux$948_Y, B=3'000, Y=$procmux$951_Y New ports: A=$procmux$948_Y [0], B=1'0, Y=$procmux$951_Y [0] New connections: $procmux$951_Y [2:1] = { $procmux$951_Y [0] $procmux$951_Y [0] } Consolidated identical input bits for $mux cell $procmux$971: Old ports: A=$procmux$948_Y, B=3'111, Y=$procmux$971_Y New ports: A=$procmux$948_Y [0], B=1'1, Y=$procmux$971_Y [0] New connections: $procmux$971_Y [2:1] = { $procmux$971_Y [0] $procmux$971_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $procmux$953: Old ports: A=3'000, B=$procmux$951_Y, Y=$0\vga_b_r[2:0] New ports: A=1'0, B=$procmux$951_Y [0], Y=$0\vga_b_r[2:0] [0] New connections: $0\vga_b_r[2:0] [2:1] = { $0\vga_b_r[2:0] [0] $0\vga_b_r[2:0] [0] } Consolidated identical input bits for $mux cell $procmux$973: Old ports: A=3'000, B=$procmux$971_Y, Y=$0\vga_r_r[2:0] New ports: A=1'0, B=$procmux$971_Y [0], Y=$0\vga_r_r[2:0] [0] New connections: $0\vga_r_r[2:0] [2:1] = { $0\vga_r_r[2:0] [0] $0\vga_r_r[2:0] [0] } Optimizing cells in module \top. Performed a total of 6 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.6. Executing OPT_RMDFF pass (remove dff with constant values). Removing $memory\sq_figure[19]$1890 ($dff) from module top. Removing $memory\sq_figure[18]$1888 ($dff) from module top. Removing $memory\sq_figure[17]$1886 ($dff) from module top. Removing $memory\sq_figure[16]$1884 ($dff) from module top. Removing $memory\sq_figure[15]$1882 ($dff) from module top. Removing $memory\sq_figure[14]$1880 ($dff) from module top. Removing $memory\sq_figure[13]$1878 ($dff) from module top. Removing $memory\sq_figure[12]$1876 ($dff) from module top. Removing $memory\sq_figure[7]$1866 ($dff) from module top. Removing $memory\sq_figure[6]$1864 ($dff) from module top. Removing $memory\sq_figure[5]$1862 ($dff) from module top. Removing $memory\sq_figure[4]$1860 ($dff) from module top. Removing $memory\sq_figure[3]$1858 ($dff) from module top. Removing $memory\sq_figure[2]$1856 ($dff) from module top. Removing $memory\sq_figure[1]$1854 ($dff) from module top. Removing $memory\sq_figure[0]$1852 ($dff) from module top. Replaced 16 DFF cells. 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$mux' cell `$memory\sq_figure$wrmux[0][0][0]$2367'. removing unused `$mux' cell `$memory\sq_figure$wrmux[1][1][0]$2517'. removing unused `$mux' cell `$memory\sq_figure$wrmux[2][2][0]$2653'. removing unused `$mux' cell `$memory\sq_figure$wrmux[3][3][0]$2789'. removing unused `$mux' cell `$memory\sq_figure$wrmux[4][4][0]$2919'. removing unused `$mux' cell `$memory\sq_figure$wrmux[5][5][0]$3051'. removing unused `$mux' cell `$memory\sq_figure$wrmux[6][6][0]$3177'. removing unused `$mux' cell `$memory\sq_figure$wrmux[7][7][0]$3303'. removing unused `$mux' cell `$memory\sq_figure$wrmux[12][8][0]$3925'. removing unused `$mux' cell `$memory\sq_figure$wrmux[13][9][0]$4055'. removing unused `$mux' cell `$memory\sq_figure$wrmux[14][10][0]$4181'. removing unused `$mux' cell `$memory\sq_figure$wrmux[15][11][0]$4307'. removing unused `$mux' cell `$memory\sq_figure$wrmux[16][12][0]$4441'. removing unused `$mux' cell `$memory\sq_figure$wrmux[17][13][0]$4569'. removing unused `$mux' cell `$memory\sq_figure$wrmux[18][14][0]$4695'. removing unused `$mux' cell `$memory\sq_figure$wrmux[19][15][0]$4821'. removing unused non-port wire \sq_figure[19]. removing unused non-port wire \sq_figure[18]. removing unused non-port wire \sq_figure[17]. removing unused non-port wire \sq_figure[16]. removing unused non-port wire \sq_figure[15]. removing unused non-port wire \sq_figure[14]. removing unused non-port wire \sq_figure[13]. removing unused non-port wire \sq_figure[12]. removing unused non-port wire \sq_figure[7]. removing unused non-port wire \sq_figure[6]. removing unused non-port wire \sq_figure[5]. removing unused non-port wire \sq_figure[4]. removing unused non-port wire \sq_figure[3]. removing unused non-port wire \sq_figure[2]. removing unused non-port wire \sq_figure[1]. removing unused non-port wire \sq_figure[0]. removed 1571 unused temporary wires. Removed 52 unused cells and 2407 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). Replacing $mux cell `$memory\sq_figure$rdmux[0][4][3]$1946' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][1]$b$1918 = 20'01111111111111111100'. Replacing $mux cell `$memory\sq_figure$rdmux[0][4][2]$1943' (?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][1]$a$1917 = 20'00111111111111111000'. 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $memory\sq_figure$rdmux[0][0][0]$1892 (pure) Root of a mux tree: $memory\sq_figure$wrmux[10][18][0]$3739 (pure) Root of a mux tree: $memory\sq_figure$wrmux[11][19][0]$3865 (pure) Root of a mux tree: $memory\sq_figure$wrmux[8][16][0]$3487 (pure) Root of a mux tree: $memory\sq_figure$wrmux[9][17][0]$3613 (pure) Root of a mux tree: $procmux$229 Root of a mux tree: $procmux$247 (pure) Root of a mux tree: $procmux$262 Root of a mux tree: $procmux$280 (pure) Root of a mux tree: $procmux$289 Root of a mux tree: $procmux$307 (pure) Root of a mux tree: $procmux$313 Root of a mux tree: $procmux$331 (pure) Root of a mux tree: $procmux$337 Root of a mux tree: $procmux$355 (pure) Root of a mux tree: $procmux$361 Root of a mux tree: $procmux$379 (pure) Root of a mux tree: $procmux$385 Root of a mux tree: $procmux$403 (pure) Root of a mux tree: $procmux$409 Root of a mux tree: $procmux$427 (pure) Root of a mux tree: $procmux$659 Root of a mux tree: $procmux$667 Root of a mux tree: $procmux$680 Root of a mux tree: $procmux$695 (pure) Root of a mux tree: $procmux$702 Root of a mux tree: $procmux$710 Root of a mux tree: $procmux$717 Root of a mux tree: $procmux$728 Root of a mux tree: $procmux$738 (pure) Removing pure flag from root mux $procmux$702. Root of a mux tree: $procmux$745 Root of a mux tree: $procmux$753 Root of a mux tree: $procmux$766 Root of a mux tree: $procmux$781 (pure) Root of a mux tree: $procmux$788 Root of a mux tree: $procmux$796 Root of a mux tree: $procmux$803 Root of a mux tree: $procmux$814 Root of a mux tree: $procmux$824 (pure) Removing pure flag from root mux $procmux$788. Root of a mux tree: $procmux$827 (pure) Root of a mux tree: $procmux$839 (pure) Root of a mux tree: $procmux$854 (pure) Root of a mux tree: $procmux$857 Root of a mux tree: $procmux$864 Root of a mux tree: $procmux$872 (pure) Root of a mux tree: $procmux$875 Root of a mux tree: $procmux$882 Root of a mux tree: $procmux$890 (pure) Root of a mux tree: $procmux$905 (pure) Root of a mux tree: $procmux$911 (pure) Root of a mux tree: $procmux$917 (pure) Root of a mux tree: $procmux$923 (pure) Root of a mux tree: $procmux$929 (pure) Root of a mux tree: $procmux$935 (pure) Root of a mux tree: $procmux$948 Root of a mux tree: $procmux$953 (pure) Root of a mux tree: $procmux$973 (pure) Root of a mux tree: $procmux$788 (rerun as non-pure) Root of a mux tree: $procmux$702 (rerun as non-pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][3][1]$1916: Old ports: A=$memory\sq_figure$rdmux[0][3][1]$a$1917, B=$memory\sq_figure$rdmux[0][3][1]$b$1918, Y=$memory\sq_figure$rdmux[0][2][0]$b$1903 New ports: A=1'0, B=1'1, Y=$memory\sq_figure$rdmux[0][2][0]$b$1903 [2] New connections: { $memory\sq_figure$rdmux[0][2][0]$b$1903 [19:3] $memory\sq_figure$rdmux[0][2][0]$b$1903 [1:0] } = { 1'0 $memory\sq_figure$rdmux[0][2][0]$b$1903 [2] 17'11111111111111100 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][4][0]$1937: Old ports: A=20'00000000000000000000, B=20'00000001111100000000, Y=$memory\sq_figure$rdmux[0][3][0]$a$1914 New ports: A=1'0, B=1'1, Y=$memory\sq_figure$rdmux[0][3][0]$a$1914 [8] New connections: { $memory\sq_figure$rdmux[0][3][0]$a$1914 [19:9] $memory\sq_figure$rdmux[0][3][0]$a$1914 [7:0] } = { 7'0000000 $memory\sq_figure$rdmux[0][3][0]$a$1914 [8] $memory\sq_figure$rdmux[0][3][0]$a$1914 [8] $memory\sq_figure$rdmux[0][3][0]$a$1914 [8] $memory\sq_figure$rdmux[0][3][0]$a$1914 [8] 8'00000000 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][4][1]$1940: Old ports: A=20'00000111111111000000, B=20'00011111111111110000, Y=$memory\sq_figure$rdmux[0][3][0]$b$1915 New ports: A=1'0, B=1'1, Y=$memory\sq_figure$rdmux[0][3][0]$b$1915 [4] New connections: { $memory\sq_figure$rdmux[0][3][0]$b$1915 [19:5] $memory\sq_figure$rdmux[0][3][0]$b$1915 [3:0] } = { 3'000 $memory\sq_figure$rdmux[0][3][0]$b$1915 [4] $memory\sq_figure$rdmux[0][3][0]$b$1915 [4] 9'111111111 $memory\sq_figure$rdmux[0][3][0]$b$1915 [4] 4'0000 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][4][6]$1955: Old ports: A=20'11111111111111111110, B=20'01111111111111111100, Y=$memory\sq_figure$rdmux[0][3][3]$a$1923 New ports: A=1'1, B=1'0, Y=$memory\sq_figure$rdmux[0][3][3]$a$1923 [1] New connections: { $memory\sq_figure$rdmux[0][3][3]$a$1923 [19:2] $memory\sq_figure$rdmux[0][3][3]$a$1923 [0] } = { $memory\sq_figure$rdmux[0][3][3]$a$1923 [1] 18'111111111111111110 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][4][7]$1958: Old ports: A=20'01111111111111111100, B=20'00111111111111111000, Y=$memory\sq_figure$rdmux[0][3][3]$b$1924 New ports: A=1'1, B=1'0, Y=$memory\sq_figure$rdmux[0][3][3]$b$1924 [2] New connections: { $memory\sq_figure$rdmux[0][3][3]$b$1924 [19:3] $memory\sq_figure$rdmux[0][3][3]$b$1924 [1:0] } = { 1'0 $memory\sq_figure$rdmux[0][3][3]$b$1924 [2] 17'11111111111111100 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][4][8]$1961: Old ports: A=20'00111111111111111000, B=20'00011111111111110000, Y=$memory\sq_figure$rdmux[0][3][4]$a$1926 New ports: A=1'1, B=1'0, Y=$memory\sq_figure$rdmux[0][3][4]$a$1926 [3] New connections: { $memory\sq_figure$rdmux[0][3][4]$a$1926 [19:4] $memory\sq_figure$rdmux[0][3][4]$a$1926 [2:0] } = { 2'00 $memory\sq_figure$rdmux[0][3][4]$a$1926 [3] 16'1111111111111000 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][4][9]$1964: Old ports: A=20'00000111111111000000, B=20'00000001111100000000, Y=$memory\sq_figure$rdmux[0][3][4]$b$1927 New ports: A=1'1, B=1'0, Y=$memory\sq_figure$rdmux[0][3][4]$b$1927 [6] New connections: { $memory\sq_figure$rdmux[0][3][4]$b$1927 [19:7] $memory\sq_figure$rdmux[0][3][4]$b$1927 [5:0] } = { 5'00000 $memory\sq_figure$rdmux[0][3][4]$b$1927 [6] $memory\sq_figure$rdmux[0][3][4]$b$1927 [6] 5'11111 $memory\sq_figure$rdmux[0][3][4]$b$1927 [6] 6'000000 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][3][0]$1913: Old ports: A=$memory\sq_figure$rdmux[0][3][0]$a$1914, B=$memory\sq_figure$rdmux[0][3][0]$b$1915, Y=$memory\sq_figure$rdmux[0][2][0]$a$1902 New ports: A={ $memory\sq_figure$rdmux[0][3][0]$a$1914 [8] 2'00 }, B={ 2'11 $memory\sq_figure$rdmux[0][3][0]$b$1915 [4] }, Y={ $memory\sq_figure$rdmux[0][2][0]$a$1902 [8] $memory\sq_figure$rdmux[0][2][0]$a$1902 [6] $memory\sq_figure$rdmux[0][2][0]$a$1902 [4] } New connections: { $memory\sq_figure$rdmux[0][2][0]$a$1902 [19:9] $memory\sq_figure$rdmux[0][2][0]$a$1902 [7] $memory\sq_figure$rdmux[0][2][0]$a$1902 [5] $memory\sq_figure$rdmux[0][2][0]$a$1902 [3:0] } = { 3'000 $memory\sq_figure$rdmux[0][2][0]$a$1902 [4] $memory\sq_figure$rdmux[0][2][0]$a$1902 [4] $memory\sq_figure$rdmux[0][2][0]$a$1902 [6] $memory\sq_figure$rdmux[0][2][0]$a$1902 [6] $memory\sq_figure$rdmux[0][2][0]$a$1902 [8] $memory\sq_figure$rdmux[0][2][0]$a$1902 [8] $memory\sq_figure$rdmux[0][2][0]$a$1902 [8] $memory\sq_figure$rdmux[0][2][0]$a$1902 [8] $memory\sq_figure$rdmux[0][2][0]$a$1902 [6] $memory\sq_figure$rdmux[0][2][0]$a$1902 [4] 4'0000 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][3][3]$1922: Old ports: A=$memory\sq_figure$rdmux[0][3][3]$a$1923, B=$memory\sq_figure$rdmux[0][3][3]$b$1924, Y=$memory\sq_figure$rdmux[0][2][1]$b$1906 New ports: A={ 1'1 $memory\sq_figure$rdmux[0][3][3]$a$1923 [1] }, B={ $memory\sq_figure$rdmux[0][3][3]$b$1924 [2] 1'0 }, Y=$memory\sq_figure$rdmux[0][2][1]$b$1906 [2:1] New connections: { $memory\sq_figure$rdmux[0][2][1]$b$1906 [19:3] $memory\sq_figure$rdmux[0][2][1]$b$1906 [0] } = { $memory\sq_figure$rdmux[0][2][1]$b$1906 [1] $memory\sq_figure$rdmux[0][2][1]$b$1906 [2] 16'1111111111111110 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][3][4]$1925: Old ports: A=$memory\sq_figure$rdmux[0][3][4]$a$1926, B=$memory\sq_figure$rdmux[0][3][4]$b$1927, Y=$memory\sq_figure$rdmux[0][2][2]$a$1908 New ports: A={ 2'11 $memory\sq_figure$rdmux[0][3][4]$a$1926 [3] }, B={ $memory\sq_figure$rdmux[0][3][4]$b$1927 [6] 2'00 }, Y={ $memory\sq_figure$rdmux[0][2][2]$a$1908 [6] $memory\sq_figure$rdmux[0][2][2]$a$1908 [4:3] } New connections: { $memory\sq_figure$rdmux[0][2][2]$a$1908 [19:7] $memory\sq_figure$rdmux[0][2][2]$a$1908 [5] $memory\sq_figure$rdmux[0][2][2]$a$1908 [2:0] } = { 2'00 $memory\sq_figure$rdmux[0][2][2]$a$1908 [3] $memory\sq_figure$rdmux[0][2][2]$a$1908 [4] $memory\sq_figure$rdmux[0][2][2]$a$1908 [4] $memory\sq_figure$rdmux[0][2][2]$a$1908 [6] $memory\sq_figure$rdmux[0][2][2]$a$1908 [6] 5'11111 $memory\sq_figure$rdmux[0][2][2]$a$1908 [6] $memory\sq_figure$rdmux[0][2][2]$a$1908 [4] 3'000 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][2][0]$1901: Old ports: A=$memory\sq_figure$rdmux[0][2][0]$a$1902, B={ 1'0 $memory\sq_figure$rdmux[0][2][0]$b$1903 [2] 15'111111111111111 $memory\sq_figure$rdmux[0][2][0]$b$1903 [2] 2'00 }, Y=$memory\sq_figure$rdmux[0][1][0]$a$1896 New ports: A={ $memory\sq_figure$rdmux[0][2][0]$a$1902 [8] $memory\sq_figure$rdmux[0][2][0]$a$1902 [6] $memory\sq_figure$rdmux[0][2][0]$a$1902 [4] 2'00 }, B={ 4'1111 $memory\sq_figure$rdmux[0][2][0]$b$1903 [2] }, Y={ $memory\sq_figure$rdmux[0][1][0]$a$1896 [8] $memory\sq_figure$rdmux[0][1][0]$a$1896 [6] $memory\sq_figure$rdmux[0][1][0]$a$1896 [4:2] } New connections: { $memory\sq_figure$rdmux[0][1][0]$a$1896 [19:9] $memory\sq_figure$rdmux[0][1][0]$a$1896 [7] $memory\sq_figure$rdmux[0][1][0]$a$1896 [5] $memory\sq_figure$rdmux[0][1][0]$a$1896 [1:0] } = { 1'0 $memory\sq_figure$rdmux[0][1][0]$a$1896 [2] $memory\sq_figure$rdmux[0][1][0]$a$1896 [3] $memory\sq_figure$rdmux[0][1][0]$a$1896 [4] $memory\sq_figure$rdmux[0][1][0]$a$1896 [4] $memory\sq_figure$rdmux[0][1][0]$a$1896 [6] $memory\sq_figure$rdmux[0][1][0]$a$1896 [6] $memory\sq_figure$rdmux[0][1][0]$a$1896 [8] $memory\sq_figure$rdmux[0][1][0]$a$1896 [8] $memory\sq_figure$rdmux[0][1][0]$a$1896 [8] $memory\sq_figure$rdmux[0][1][0]$a$1896 [8] $memory\sq_figure$rdmux[0][1][0]$a$1896 [6] $memory\sq_figure$rdmux[0][1][0]$a$1896 [4] 2'00 } Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][2][2]$1907: Old ports: A=$memory\sq_figure$rdmux[0][2][2]$a$1908, B=20'xxxxxxxxxxxxxxxxxxxx, Y=$memory\sq_figure$rdmux[0][1][1]$a$1899 New ports: A={ 1'1 $memory\sq_figure$rdmux[0][2][2]$a$1908 [6] $memory\sq_figure$rdmux[0][2][2]$a$1908 [4:3] 1'0 }, B=5'xxxxx, Y={ $memory\sq_figure$rdmux[0][1][1]$a$1899 [8] $memory\sq_figure$rdmux[0][1][1]$a$1899 [6] $memory\sq_figure$rdmux[0][1][1]$a$1899 [4:3] $memory\sq_figure$rdmux[0][1][1]$a$1899 [0] } New connections: { $memory\sq_figure$rdmux[0][1][1]$a$1899 [19:9] $memory\sq_figure$rdmux[0][1][1]$a$1899 [7] $memory\sq_figure$rdmux[0][1][1]$a$1899 [5] $memory\sq_figure$rdmux[0][1][1]$a$1899 [2:1] } = { $memory\sq_figure$rdmux[0][1][1]$a$1899 [0] $memory\sq_figure$rdmux[0][1][1]$a$1899 [0] $memory\sq_figure$rdmux[0][1][1]$a$1899 [3] $memory\sq_figure$rdmux[0][1][1]$a$1899 [4] $memory\sq_figure$rdmux[0][1][1]$a$1899 [4] $memory\sq_figure$rdmux[0][1][1]$a$1899 [6] $memory\sq_figure$rdmux[0][1][1]$a$1899 [6] $memory\sq_figure$rdmux[0][1][1]$a$1899 [8] $memory\sq_figure$rdmux[0][1][1]$a$1899 [8] $memory\sq_figure$rdmux[0][1][1]$a$1899 [8] $memory\sq_figure$rdmux[0][1][1]$a$1899 [8] $memory\sq_figure$rdmux[0][1][1]$a$1899 [6] $memory\sq_figure$rdmux[0][1][1]$a$1899 [4] $memory\sq_figure$rdmux[0][1][1]$a$1899 [0] $memory\sq_figure$rdmux[0][1][1]$a$1899 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory\sq_figure$rdmux[0][1][1]$1898: Old ports: A=$memory\sq_figure$rdmux[0][1][1]$a$1899, B=20'xxxxxxxxxxxxxxxxxxxx, Y=$memory\sq_figure$rdmux[0][0][0]$b$1894 New ports: A={ $memory\sq_figure$rdmux[0][1][1]$a$1899 [8] $memory\sq_figure$rdmux[0][1][1]$a$1899 [6] $memory\sq_figure$rdmux[0][1][1]$a$1899 [4:3] $memory\sq_figure$rdmux[0][1][1]$a$1899 [0] }, B=5'xxxxx, Y={ $memory\sq_figure$rdmux[0][0][0]$b$1894 [8] $memory\sq_figure$rdmux[0][0][0]$b$1894 [6] $memory\sq_figure$rdmux[0][0][0]$b$1894 [4:3] $memory\sq_figure$rdmux[0][0][0]$b$1894 [0] } New connections: { $memory\sq_figure$rdmux[0][0][0]$b$1894 [19:9] $memory\sq_figure$rdmux[0][0][0]$b$1894 [7] $memory\sq_figure$rdmux[0][0][0]$b$1894 [5] $memory\sq_figure$rdmux[0][0][0]$b$1894 [2:1] } = { $memory\sq_figure$rdmux[0][0][0]$b$1894 [0] $memory\sq_figure$rdmux[0][0][0]$b$1894 [0] $memory\sq_figure$rdmux[0][0][0]$b$1894 [3] $memory\sq_figure$rdmux[0][0][0]$b$1894 [4] $memory\sq_figure$rdmux[0][0][0]$b$1894 [4] $memory\sq_figure$rdmux[0][0][0]$b$1894 [6] $memory\sq_figure$rdmux[0][0][0]$b$1894 [6] $memory\sq_figure$rdmux[0][0][0]$b$1894 [8] $memory\sq_figure$rdmux[0][0][0]$b$1894 [8] $memory\sq_figure$rdmux[0][0][0]$b$1894 [8] $memory\sq_figure$rdmux[0][0][0]$b$1894 [8] $memory\sq_figure$rdmux[0][0][0]$b$1894 [6] $memory\sq_figure$rdmux[0][0][0]$b$1894 [4] $memory\sq_figure$rdmux[0][0][0]$b$1894 [0] $memory\sq_figure$rdmux[0][0][0]$b$1894 [0] } Optimizing cells in module \top. Performed a total of 13 changes. 2.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$memory\sq_figure$rdmux[0][4][1]$1940' is identical to cell `$memory\sq_figure$rdmux[0][4][0]$1937'. Redirecting output \Y: $memory\sq_figure$rdmux[0][3][0]$b$1915 [4] = $memory\sq_figure$rdmux[0][3][0]$a$1914 [8] Removing $mux cell `$memory\sq_figure$rdmux[0][4][1]$1940' from module `\top'. Cell `$memory\sq_figure$rdmux[0][4][7]$1958' is identical to cell `$memory\sq_figure$rdmux[0][4][6]$1955'. Redirecting output \Y: $memory\sq_figure$rdmux[0][3][3]$b$1924 [2] = $memory\sq_figure$rdmux[0][3][3]$a$1923 [1] Removing $mux cell `$memory\sq_figure$rdmux[0][4][7]$1958' from module `\top'. Cell `$memory\sq_figure$rdmux[0][4][8]$1961' is identical to cell `$memory\sq_figure$rdmux[0][4][6]$1955'. Redirecting output \Y: $memory\sq_figure$rdmux[0][3][4]$a$1926 [3] = $memory\sq_figure$rdmux[0][3][3]$a$1923 [1] Removing $mux cell `$memory\sq_figure$rdmux[0][4][8]$1961' from module `\top'. Cell `$memory\sq_figure$rdmux[0][4][9]$1964' is identical to cell `$memory\sq_figure$rdmux[0][4][6]$1955'. Redirecting output \Y: $memory\sq_figure$rdmux[0][3][4]$b$1927 [6] = $memory\sq_figure$rdmux[0][3][3]$a$1923 [1] Removing $mux cell `$memory\sq_figure$rdmux[0][4][9]$1964' from module `\top'. Removed a total of 4 cells. 2.12.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removed 6 unused temporary wires. Removed 52 unused cells and 2413 unused wires. 2.12.15. Executing OPT_EXPR pass (perform const folding). 2.12.16. Rerunning OPT passes. (Maybe there is more to do..) 2.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $memory\sq_figure$rdmux[0][0][0]$1892 (pure) Root of a mux tree: $memory\sq_figure$rdmux[0][4][6]$1955 Root of a mux tree: $memory\sq_figure$wrmux[10][18][0]$3739 (pure) Root of a mux tree: $memory\sq_figure$wrmux[11][19][0]$3865 (pure) Root of a mux tree: $memory\sq_figure$wrmux[8][16][0]$3487 (pure) Root of a mux tree: $memory\sq_figure$wrmux[9][17][0]$3613 (pure) Root of a mux tree: $procmux$229 Root of a mux tree: $procmux$247 (pure) Root of a mux tree: $procmux$262 Root of a mux tree: $procmux$280 (pure) Root of a mux tree: $procmux$289 Root of a mux tree: $procmux$307 (pure) Root of a mux tree: $procmux$313 Root of a mux tree: $procmux$331 (pure) Root of a mux tree: $procmux$337 Root of a mux tree: $procmux$355 (pure) Root of a mux tree: $procmux$361 Root of a mux tree: $procmux$379 (pure) Root of a mux tree: $procmux$385 Root of a mux tree: $procmux$403 (pure) Root of a mux tree: $procmux$409 Root of a mux tree: $procmux$427 (pure) Root of a mux tree: $procmux$659 Root of a mux tree: $procmux$667 Root of a mux tree: $procmux$680 Root of a mux tree: $procmux$695 (pure) Root of a mux tree: $procmux$702 Root of a mux tree: $procmux$710 Root of a mux tree: $procmux$717 Root of a mux tree: $procmux$728 Root of a mux tree: $procmux$738 (pure) Removing pure flag from root mux $procmux$702. Root of a mux tree: $procmux$745 Root of a mux tree: $procmux$753 Root of a mux tree: $procmux$766 Root of a mux tree: $procmux$781 (pure) Root of a mux tree: $procmux$788 Root of a mux tree: $procmux$796 Root of a mux tree: $procmux$803 Root of a mux tree: $procmux$814 Root of a mux tree: $procmux$824 (pure) Removing pure flag from root mux $procmux$788. Root of a mux tree: $procmux$827 (pure) Root of a mux tree: $procmux$839 (pure) Root of a mux tree: $procmux$854 (pure) Root of a mux tree: $procmux$857 Root of a mux tree: $procmux$864 Root of a mux tree: $procmux$872 (pure) Root of a mux tree: $procmux$875 Root of a mux tree: $procmux$882 Root of a mux tree: $procmux$890 (pure) Root of a mux tree: $procmux$905 (pure) Root of a mux tree: $procmux$911 (pure) Root of a mux tree: $procmux$917 (pure) Root of a mux tree: $procmux$923 (pure) Root of a mux tree: $procmux$929 (pure) Root of a mux tree: $procmux$935 (pure) Root of a mux tree: $procmux$948 Root of a mux tree: $procmux$953 (pure) Root of a mux tree: $procmux$973 (pure) Root of a mux tree: $procmux$788 (rerun as non-pure) Root of a mux tree: $procmux$702 (rerun as non-pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.20. Executing OPT_RMDFF pass (remove dff with constant values). 2.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 52 unused cells and 2413 unused wires. 2.12.22. Executing OPT_EXPR pass (perform const folding). 2.12.23. Finished OPT passes. (There is nothing left to do.) 2.13. Executing TECHMAP pass (map to technology primitives). 2.13.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.13.2. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. Mapping top.$auto$alumacc.cc:78:get_cf$1188 ($not) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][4][0]$1937 ($mux) with simplemap. 2.13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 9 Parameter \B_WIDTH = 10 Parameter \Y_WIDTH = 10 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=10\Y_WIDTH=10'. 2.13.4. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1153 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$memory_share.cc:346:merge_en_data$1390 ($not) with simplemap. Mapping top.$auto$memory_share.cc:346:merge_en_data$1392 ($and) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$1156 ($reduce_and) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1158 ($not) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1160 ($or) with simplemap. Mapping top.$auto$opt_expr.cc:158:group_cell_inputs$1845 ($or) with simplemap. 2.13.5. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 4 Parameter \B_WIDTH = 10 Parameter \Y_WIDTH = 10 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10'. 2.13.6. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1259 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10. 2.13.7. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 10 Parameter \B_WIDTH = 10 Parameter \Y_WIDTH = 10 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10'. 2.13.8. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1164 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:78:get_cf$1167 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1251 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:474:replace_alu$1169 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:78:get_cf$1172 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1174 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:64:get_eq$1177 ($reduce_and) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1179 ($not) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1181 ($or) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][1][0]$1895 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1183 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1185 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$memory_share.cc:340:merge_en_data$1494 ($and) with simplemap. Mapping top.$auto$memory_share.cc:340:merge_en_data$1492 ($not) with simplemap. Mapping top.$auto$opt_expr.cc:158:group_cell_inputs$1831 ($or) with simplemap. Mapping top.$eq$example.v:108$38 ($eq) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1115 ($not) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1117 ($or) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1119 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1121 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:78:get_cf$1124 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1126 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$opt_expr.cc:158:group_cell_inputs$1849 ($or) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$1129 ($reduce_and) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1131 ($not) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1133 ($or) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1135 ($not) with simplemap. 2.13.9. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 8 Parameter \B_WIDTH = 8 Parameter \Y_WIDTH = 8 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. 2.13.10. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1137 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8. Mapping top.$auto$alumacc.cc:64:get_eq$1140 ($reduce_and) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1142 ($not) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1144 ($or) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][0][0]$1892 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1148 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$memory_share.cc:339:merge_en_data$1490 ($and) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][4][4]$1949 ($mux) with simplemap. Mapping top.$logic_or$example.v:168$126 ($logic_or) with simplemap. Mapping top.$logic_or$example.v:174$129 ($logic_or) with simplemap. Mapping top.$auto$memory_share.cc:339:merge_en_data$1376 ($and) with simplemap. Mapping top.$logic_and$example.v:186$134 ($logic_and) with simplemap. Mapping top.$logic_and$example.v:192$137 ($logic_and) with simplemap. Mapping top.$eq$example.v:193$139 ($logic_not) with simplemap. Mapping top.$eq$example.v:193$140 ($logic_not) with simplemap. Mapping top.$logic_or$example.v:193$141 ($logic_or) with simplemap. Mapping top.$eq$example.v:193$142 ($eq) with simplemap. Mapping top.$logic_or$example.v:193$143 ($logic_or) with simplemap. Mapping top.$eq$example.v:193$144 ($eq) with simplemap. Mapping top.$logic_or$example.v:193$145 ($logic_or) with simplemap. Mapping top.$auto$memory_share.cc:325:merge_en_data$1368 ($or) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][1][1]$1898 ($mux) with simplemap. Mapping top.$auto$memory_share.cc:340:merge_en_data$1378 ($not) with simplemap. Mapping top.$logic_and$example.v:198$149 ($logic_and) with simplemap. Mapping top.$logic_and$example.v:198$151 ($logic_and) with simplemap. Mapping top.$logic_and$example.v:198$153 ($logic_and) with simplemap. 2.13.11. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 10 Parameter \B_WIDTH = 4 Parameter \Y_WIDTH = 10 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=4\Y_WIDTH=10'. 2.13.12. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1274 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=4\Y_WIDTH=10. 2.13.13. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 5 Parameter \B_WIDTH = 5 Parameter \Y_WIDTH = 5 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. 2.13.14. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1262 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5. 2.13.15. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_shift_shiftx'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 20 Parameter \B_WIDTH = 5 Parameter \Y_WIDTH = 1 Parameter \_TECHMAP_CELLTYPE_ = 56'00100100011100110110100001101001011001100111010001111000 Generating RTLIL representation for module `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx'. 2.13.16. Executing PROC pass (convert processes to netlists). 2.13.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 11 empty switches in `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.$proc$/usr/local/bin/../share/yosys/techmap.v:145$5353'. Cleaned up 11 empty switches. 2.13.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.13.16.3. Executing PROC_INIT pass (extract init attributes). 2.13.16.4. Executing PROC_ARST pass (detect async resets in processes). 2.13.16.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.$proc$/usr/local/bin/../share/yosys/techmap.v:145$5353'. 1/17: $15\buffer[19:0] 2/17: $14\buffer[19:0] 3/17: $13\buffer[19:0] 4/17: $12\buffer[19:0] 5/17: $11\buffer[19:0] 6/17: $10\buffer[19:0] 7/17: $9\buffer[19:0] 8/17: $8\buffer[19:0] 9/17: $7\buffer[19:0] 10/17: $6\buffer[19:0] 11/17: $5\buffer[19:0] 12/17: $4\buffer[19:0] 13/17: $3\buffer[19:0] 14/17: $2\buffer[19:0] 15/17: $1\buffer[19:0] 16/17: $0\buffer[19:0] 17/17: $0\overflow[0:0] 2.13.16.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.\buffer' from process `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.$proc$/usr/local/bin/../share/yosys/techmap.v:145$5353'. No latch inferred for signal `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.\overflow' from process `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.$proc$/usr/local/bin/../share/yosys/techmap.v:145$5353'. 2.13.16.7. Executing PROC_DFF pass (convert process syncs to FFs). 2.13.16.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 5 empty switches in `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.$proc$/usr/local/bin/../share/yosys/techmap.v:145$5353'. Removing empty process `$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.$proc$/usr/local/bin/../share/yosys/techmap.v:145$5353'. Cleaned up 5 empty switches. Removed 0 unused cells and 35 unused wires. Analyzing pattern of constant bits for this cell: Creating constmapped module `$paramod$constmap:2b38e406732613cd884da597c99291ccae15b378$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx'. 2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$constmap:2b38e406732613cd884da597c99291ccae15b378$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$5397 Root of a mux tree: $procmux$5388 Root of a mux tree: $procmux$5379 Root of a mux tree: $procmux$5370 Root of a mux tree: $procmux$5361 (pure) Removing pure flag from root mux $procmux$5397. Root of a mux tree: $procmux$5397 (rerun as non-pure) Analyzing evaluation results. dead port 2/2 on $mux $procmux$5394. dead port 2/2 on $mux $procmux$5391. dead port 2/2 on $mux $procmux$5385. dead port 2/2 on $mux $procmux$5382. dead port 2/2 on $mux $procmux$5376. dead port 2/2 on $mux $procmux$5373. dead port 2/2 on $mux $procmux$5367. dead port 2/2 on $mux $procmux$5364. dead port 2/2 on $mux $procmux$5358. dead port 2/2 on $mux $procmux$5355. Removed 10 multiplexer ports. 2.13.18. Executing OPT_EXPR pass (perform const folding). Removed 0 unused cells and 11 unused wires. 2.13.19. Continuing TECHMAP pass. Mapping top.$shiftx$example.v:202$156 using $paramod$constmap:2b38e406732613cd884da597c99291ccae15b378$paramod$62c9c76a487bbb65c8d42fc373587bfe2c574c75\_90_shift_shiftx. Mapping top.$eq$example.v:225$158 ($eq) with simplemap. Mapping top.$eq$example.v:225$159 ($eq) with simplemap. Mapping top.$logic_and$example.v:225$160 ($logic_and) with simplemap. Mapping top.$auto$memory_share.cc:340:merge_en_data$1380 ($and) with simplemap. Mapping top.$eq$example.v:271$171 ($eq) with simplemap. Mapping top.$eq$example.v:304$173 ($logic_not) with simplemap. Mapping top.$xor$example.v:306$179 ($xor) with simplemap. Mapping top.$xor$example.v:307$181 ($xor) with simplemap. Mapping top.$xor$example.v:308$183 ($xor) with simplemap. Mapping top.$xor$example.v:309$185 ($xor) with simplemap. Mapping top.$eq$example.v:312$186 ($eq) with simplemap. Mapping top.$eq$example.v:313$187 ($eq) with simplemap. Mapping top.$eq$example.v:326$189 ($eq) with simplemap. Mapping top.$eq$example.v:339$191 ($eq) with simplemap. Mapping top.$eq$example.v:352$193 ($eq) with simplemap. Mapping top.$procmux$227 ($mux) with simplemap. Mapping top.$procmux$229 ($mux) with simplemap. Mapping top.$procmux$234 ($mux) with simplemap. Mapping top.$procmux$237 ($mux) with simplemap. Mapping top.$procmux$240 ($mux) with simplemap. Mapping top.$procmux$243 ($mux) with simplemap. Mapping top.$procmux$245 ($mux) with simplemap. Mapping top.$procmux$247 ($mux) with simplemap. Mapping top.$procmux$260 ($mux) with simplemap. Mapping top.$procmux$262 ($mux) with simplemap. Mapping top.$procmux$267 ($mux) with simplemap. Mapping top.$procmux$270 ($mux) with simplemap. Mapping top.$procmux$273 ($mux) with simplemap. Mapping top.$procmux$276 ($mux) with simplemap. Mapping top.$procmux$278 ($mux) with simplemap. Mapping top.$procmux$280 ($mux) with simplemap. Mapping top.$procmux$287 ($mux) with simplemap. Mapping top.$procmux$289 ($mux) with simplemap. Mapping top.$procmux$294 ($mux) with simplemap. Mapping top.$procmux$297 ($mux) with simplemap. Mapping top.$procmux$300 ($mux) with simplemap. Mapping top.$procmux$303 ($mux) with simplemap. Mapping top.$procmux$305 ($mux) with simplemap. Mapping top.$procmux$307 ($mux) with simplemap. Mapping top.$procmux$311 ($mux) with simplemap. Mapping top.$procmux$313 ($mux) with simplemap. Mapping top.$procmux$318 ($mux) with simplemap. Mapping top.$procmux$321 ($mux) with simplemap. Mapping top.$procmux$324 ($mux) with simplemap. Mapping top.$procmux$327 ($mux) with simplemap. Mapping top.$procmux$329 ($mux) with simplemap. Mapping top.$procmux$331 ($mux) with simplemap. Mapping top.$procmux$335 ($mux) with simplemap. Mapping top.$procmux$337 ($mux) with simplemap. Mapping top.$procmux$342 ($mux) with simplemap. Mapping top.$procmux$345 ($mux) with simplemap. Mapping top.$procmux$348 ($mux) with simplemap. Mapping top.$procmux$351 ($mux) with simplemap. Mapping top.$procmux$353 ($mux) with simplemap. Mapping top.$procmux$355 ($mux) with simplemap. Mapping top.$procmux$359 ($mux) with simplemap. Mapping top.$procmux$361 ($mux) with simplemap. Mapping top.$procmux$366 ($mux) with simplemap. Mapping top.$procmux$369 ($mux) with simplemap. Mapping top.$procmux$372 ($mux) with simplemap. Mapping top.$procmux$375 ($mux) with simplemap. Mapping top.$procmux$377 ($mux) with simplemap. Mapping top.$procmux$379 ($mux) with simplemap. Mapping top.$procmux$383 ($mux) with simplemap. Mapping top.$procmux$385 ($mux) with simplemap. Mapping top.$procmux$390 ($mux) with simplemap. Mapping top.$procmux$393 ($mux) with simplemap. Mapping top.$procmux$396 ($mux) with simplemap. Mapping top.$procmux$399 ($mux) with simplemap. Mapping top.$procmux$401 ($mux) with simplemap. Mapping top.$auto$memory_share.cc:346:merge_en_data$1734 ($and) with simplemap. Mapping top.$procmux$403 ($mux) with simplemap. Mapping top.$auto$memory_share.cc:346:merge_en_data$1732 ($not) with simplemap. Mapping top.$procmux$407 ($mux) with simplemap. Mapping top.$procmux$409 ($mux) with simplemap. Mapping top.$procmux$414 ($mux) with simplemap. Mapping top.$procmux$417 ($mux) with simplemap. Mapping top.$procmux$420 ($mux) with simplemap. Mapping top.$procmux$423 ($mux) with simplemap. Mapping top.$procmux$425 ($mux) with simplemap. Mapping top.$procmux$427 ($mux) with simplemap. Mapping top.$auto$memory_share.cc:340:merge_en_data$1722 ($and) with simplemap. Mapping top.$auto$memory_share.cc:340:merge_en_data$1720 ($not) with simplemap. Mapping top.$auto$memory_share.cc:339:merge_en_data$1718 ($and) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$1113 ($reduce_and) with simplemap. Mapping top.$auto$opt_expr.cc:158:group_cell_inputs$1839 ($or) with simplemap. Mapping top.$memory\sq_figure[8]$1868 ($dff) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][3][4]$1925 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1110 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:58:get_gt$1108 ($not) with simplemap. Mapping top.$memory\sq_figure[9]$1870 ($dff) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][3][3]$1922 ($mux) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][2][0]$1901 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1106 ($or) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1104 ($not) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$1102 ($reduce_and) with simplemap. Mapping top.$memory\sq_figure[10]$1872 ($dff) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][3][2]$1919 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1277 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=4\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:474:replace_alu$1099 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$memory_share.cc:267:mask_en_naive$1640 ($not) with simplemap. Mapping top.$memory\sq_figure[11]$1874 ($dff) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][3][1]$1916 ($mux) with simplemap. Mapping top.$auto$memory_share.cc:346:merge_en_data$1620 ($and) with simplemap. Mapping top.$auto$memory_share.cc:346:merge_en_data$1618 ($not) with simplemap. Mapping top.$auto$memory_share.cc:340:merge_en_data$1608 ($and) with simplemap. Mapping top.$auto$memory_share.cc:340:merge_en_data$1606 ($not) with simplemap. Mapping top.$auto$memory_share.cc:339:merge_en_data$1604 ($and) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][3][0]$1913 ($mux) with simplemap. Mapping top.$procmux$657 ($mux) with simplemap. Mapping top.$procmux$659 ($mux) with simplemap. Mapping top.$procmux$663 ($mux) with simplemap. Mapping top.$procmux$665 ($mux) with simplemap. Mapping top.$procmux$667 ($mux) with simplemap. Mapping top.$procmux$673 ($mux) with simplemap. Mapping top.$procmux$675 ($mux) with simplemap. Mapping top.$procmux$680 ($mux) with simplemap. Mapping top.$procmux$684 ($mux) with simplemap. Mapping top.$procmux$686 ($mux) with simplemap. Mapping top.$procmux$691 ($mux) with simplemap. Mapping top.$procmux$693 ($mux) with simplemap. Mapping top.$procmux$695 ($mux) with simplemap. Mapping top.$procmux$700 ($mux) with simplemap. Mapping top.$procmux$702 ($mux) with simplemap. Mapping top.$procmux$706 ($mux) with simplemap. Mapping top.$procmux$708 ($mux) with simplemap. Mapping top.$procmux$710 ($mux) with simplemap. Mapping top.$procmux$717 ($mux) with simplemap. Mapping top.$procmux$721 ($mux) with simplemap. Mapping top.$procmux$723 ($mux) with simplemap. Mapping top.$procmux$728 ($mux) with simplemap. Mapping top.$procmux$732 ($mux) with simplemap. Mapping top.$procmux$734 ($mux) with simplemap. Mapping top.$procmux$736 ($mux) with simplemap. Mapping top.$procmux$738 ($mux) with simplemap. Mapping top.$procmux$743 ($mux) with simplemap. Mapping top.$procmux$745 ($mux) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][4][6]$1955 ($mux) with simplemap. Mapping top.$procmux$749 ($mux) with simplemap. Mapping top.$procmux$751 ($mux) with simplemap. Mapping top.$procmux$753 ($mux) with simplemap. Mapping top.$procmux$759 ($mux) with simplemap. Mapping top.$procmux$761 ($mux) with simplemap. Mapping top.$procmux$766 ($mux) with simplemap. Mapping top.$procmux$770 ($mux) with simplemap. Mapping top.$procmux$772 ($mux) with simplemap. Mapping top.$procmux$777 ($mux) with simplemap. Mapping top.$procmux$779 ($mux) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][2][2]$1907 ($mux) with simplemap. Mapping top.$procmux$781 ($mux) with simplemap. Mapping top.$procmux$786 ($mux) with simplemap. Mapping top.$procmux$788 ($mux) with simplemap. Mapping top.$procmux$792 ($mux) with simplemap. Mapping top.$procmux$794 ($mux) with simplemap. Mapping top.$procmux$796 ($mux) with simplemap. Mapping top.$procmux$803 ($mux) with simplemap. Mapping top.$procmux$807 ($mux) with simplemap. Mapping top.$procmux$809 ($mux) with simplemap. Mapping top.$procmux$814 ($mux) with simplemap. Mapping top.$procmux$818 ($mux) with simplemap. Mapping top.$procmux$820 ($mux) with simplemap. Mapping top.$procmux$822 ($mux) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][4][5]$1952 ($mux) with simplemap. Mapping top.$procmux$824 ($mux) with simplemap. Mapping top.$procmux$827 ($mux) with simplemap. Mapping top.$procmux$837 ($mux) with simplemap. Mapping top.$procmux$839 ($mux) with simplemap. Mapping top.$memory\sq_figure$rdmux[0][2][1]$1904 ($mux) with simplemap. Mapping top.$auto$memory_share.cc:346:merge_en_data$1506 ($and) with simplemap. Mapping top.$auto$memory_share.cc:346:merge_en_data$1504 ($not) with simplemap. Mapping top.$procmux$852 ($mux) with simplemap. Mapping top.$procmux$854 ($mux) with simplemap. Mapping top.$procmux$857 ($mux) with simplemap. Mapping top.$procmux$862 ($mux) with simplemap. Mapping top.$procmux$864 ($mux) with simplemap. Mapping top.$procmux$868 ($mux) with simplemap. Mapping top.$procmux$870 ($mux) with simplemap. Mapping top.$procmux$872 ($mux) with simplemap. Mapping top.$procmux$875 ($mux) with simplemap. Mapping top.$procmux$880 ($mux) with simplemap. 2.13.20. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 10 Parameter \B_WIDTH = 1 Parameter \Y_WIDTH = 10 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=1\Y_WIDTH=10'. 2.13.21. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1271 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=1\Y_WIDTH=10. Mapping top.$procmux$882 ($mux) with simplemap. Mapping top.$procmux$886 ($mux) with simplemap. Mapping top.$procmux$888 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1268 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=1\Y_WIDTH=10. Mapping top.$procmux$890 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1265 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5. Mapping top.$procmux$899 ($mux) with simplemap. Mapping top.$procmux$902 ($mux) with simplemap. Mapping top.$procmux$905 ($mux) with simplemap. Mapping top.$procmux$908 ($mux) with simplemap. Mapping top.$procmux$911 ($mux) with simplemap. Mapping top.$procmux$914 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1254 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10. Mapping top.$procmux$917 ($mux) with simplemap. Mapping top.$procmux$920 ($mux) with simplemap. Mapping top.$procmux$923 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1246 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=10\Y_WIDTH=10. Mapping top.$procmux$929 ($mux) with simplemap. 2.13.22. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 2 Parameter \Y_WIDTH = 2 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2'. Not using module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 2.13.23. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 2 Parameter \Y_WIDTH = 2 Generating RTLIL representation for module `$paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2'. 2.13.24. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1243 using $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2. Mapping top.$procmux$935 ($mux) with simplemap. 2.13.25. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 21 Parameter \Y_WIDTH = 21 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=21\Y_WIDTH=21'. 2.13.26. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1240 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=21\Y_WIDTH=21. 2.13.27. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 4 Parameter \Y_WIDTH = 4 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4'. 2.13.28. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1237 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4. Mapping top.$procmux$946 ($mux) with simplemap. Mapping top.$procmux$948 ($mux) with simplemap. Mapping top.$procmux$951 ($mux) with simplemap. 2.13.29. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 10 Parameter \Y_WIDTH = 10 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10'. 2.13.30. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1234 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10. Mapping top.$procmux$953 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1225 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:474:replace_alu$1231 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10. Mapping top.$procmux$971 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1228 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10. Mapping top.$procmux$973 ($mux) with simplemap. Mapping top.$procdff$975 ($dff) with simplemap. Mapping top.$procdff$977 ($dff) with simplemap. Mapping top.$procdff$978 ($dff) with simplemap. Mapping top.$procdff$979 ($dff) with simplemap. Mapping top.$procdff$980 ($dff) with simplemap. Mapping top.$procdff$981 ($dff) with simplemap. Mapping top.$procdff$982 ($dff) with simplemap. Mapping top.$procdff$983 ($dff) with simplemap. Mapping top.$procdff$984 ($dff) with simplemap. Mapping top.$procdff$985 ($dff) with simplemap. Mapping top.$procdff$986 ($dff) with simplemap. Mapping top.$procdff$987 ($dff) with simplemap. Mapping top.$procdff$988 ($dff) with simplemap. Mapping top.$procdff$989 ($dff) with simplemap. Mapping top.$procdff$990 ($dff) with simplemap. Mapping top.$procdff$991 ($dff) with simplemap. Mapping top.$procdff$993 ($dff) with simplemap. Mapping top.$procdff$994 ($dff) with simplemap. Mapping top.$procdff$995 ($dff) with simplemap. Mapping top.$procdff$996 ($dff) with simplemap. Mapping top.$procdff$997 ($dff) with simplemap. Mapping top.$procdff$998 ($dff) with simplemap. Mapping top.$procdff$999 ($dff) with simplemap. 2.13.31. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 8 Parameter \Y_WIDTH = 8 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8'. 2.13.32. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1222 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8. Mapping top.$auto$alumacc.cc:58:get_gt$1218 ($or) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1216 ($not) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$1214 ($reduce_and) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1211 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:474:replace_alu$1206 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:78:get_cf$1204 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1201 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10. Mapping top.$auto$alumacc.cc:58:get_gt$1199 ($not) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$1197 ($or) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$1195 ($not) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$1193 ($reduce_and) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1190 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=10\Y_WIDTH=10. Mapping top.$procdff$1077 ($dff) with simplemap. Mapping top.$memory\sq_figure$wrmux[8][16][0]$3487 ($mux) with simplemap. Mapping top.$memory\sq_figure$wrmux[9][17][0]$3613 ($mux) with simplemap. Mapping top.$memory\sq_figure$wrmux[10][18][0]$3739 ($mux) with simplemap. Mapping top.$memory\sq_figure$wrmux[11][19][0]$3865 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1228.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1225.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1228.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1231.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1231.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1225.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1234.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1234.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1237.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1237.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1237.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6554 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1237.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6555 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1237.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6556 ($xor) with simplemap. Mapping top.$techmap$shiftx$example.v:202$156.$procmux$5361 ($mux) with simplemap. Mapping top.$techmap$shiftx$example.v:202$156.$procmux$5379 ($mux) with simplemap. Mapping top.$techmap$shiftx$example.v:202$156.$procmux$5370 ($mux) with simplemap. Mapping top.$techmap$shiftx$example.v:202$156.$procmux$5397 ($mux) with simplemap. Mapping top.$techmap$shiftx$example.v:202$156.$procmux$5388 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1240.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1240.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1240.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6551 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1262.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1262.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1262.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1262.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1274.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1274.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1243.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1243.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.$not$/usr/local/bin/../share/yosys/techmap.v:258$6545 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.$ternary$/usr/local/bin/../share/yosys/techmap.v:258$6546 ($mux) with simplemap. 2.13.33. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_lcu'. Parameter \WIDTH = 2 Generating RTLIL representation for module `$paramod\_90_lcu\WIDTH=2'. 2.13.34. Executing PROC pass (convert processes to netlists). 2.13.34.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.13.34.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.13.34.3. Executing PROC_INIT pass (extract init attributes). 2.13.34.4. Executing PROC_ARST pass (detect async resets in processes). 2.13.34.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\_90_lcu\WIDTH=2.$proc$/usr/local/bin/../share/yosys/techmap.v:207$7166'. 1/4: $0\p[1:0] [1] 2/4: $0\g[1:0] [1] 3/4: $0\g[1:0] [0] 4/4: $0\p[1:0] [0] 2.13.34.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\_90_lcu\WIDTH=2.\p' from process `$paramod\_90_lcu\WIDTH=2.$proc$/usr/local/bin/../share/yosys/techmap.v:207$7166'. No latch inferred for signal `$paramod\_90_lcu\WIDTH=2.\g' from process `$paramod\_90_lcu\WIDTH=2.$proc$/usr/local/bin/../share/yosys/techmap.v:207$7166'. 2.13.34.7. Executing PROC_DFF pass (convert process syncs to FFs). 2.13.34.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\_90_lcu\WIDTH=2.$proc$/usr/local/bin/../share/yosys/techmap.v:207$7166'. Cleaned up 0 empty switches. 2.13.35. Executing OPT pass (performing simple optimizations). 2.13.35.1. Executing OPT_EXPR pass (perform const folding). 2.13.35.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\_90_lcu\WIDTH=2'. Removed a total of 0 cells. 2.13.35.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.13.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\_90_lcu\WIDTH=2.. removing unused `$and' cell `$and$/usr/local/bin/../share/yosys/techmap.v:222$7171'. removing unused non-port wire \j. removing unused non-port wire \i. removed 7 unused temporary wires. Removed 1 unused cells and 18 unused wires. 2.13.35.5. Finished fast OPT passes. 2.13.36. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$1243.lcu using $paramod\_90_lcu\WIDTH=2. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.$and$/usr/local/bin/../share/yosys/techmap.v:260$6547 ($and) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.$xor$/usr/local/bin/../share/yosys/techmap.v:262$6548 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.$xor$/usr/local/bin/../share/yosys/techmap.v:263$6549 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1246.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1246.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1254.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1254.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1148.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1148.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1265.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1265.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1265.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1265.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1137.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1137.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1268.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1268.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1126.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1126.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1271.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1271.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1121.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1121.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1185.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1185.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1174.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1174.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1169.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1169.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1169.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1251.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1251.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1164.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1164.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1164.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1259.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1259.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1099.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1099.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1099.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1277.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1277.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1153.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1153.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1153.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1110.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1110.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1110.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1222.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6702 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1222.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1222.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1211.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1211.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1211.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1206.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1206.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1206.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1201.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1201.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896 ($not) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1190.A_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$1190.B_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.lcu.$or$/usr/local/bin/../share/yosys/techmap.v:221$7170 ($or) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.lcu.$or$/usr/local/bin/../share/yosys/techmap.v:212$7168 ($or) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.lcu.$and$/usr/local/bin/../share/yosys/techmap.v:221$7169 ($and) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$1243.lcu.$and$/usr/local/bin/../share/yosys/techmap.v:212$7167 ($and) with simplemap. No more expansions possible. 2.14. Executing ICE40_OPT pass (performing simple optimizations). 2.14.1. Running ICE40 specific optimizations. 2.14.2. Executing OPT_EXPR pass (perform const folding). Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5484' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5480 [2] = \ps2_cntr [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5546' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [5] = \sq_figure[9] [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5547' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [6] = \sq_figure[9] [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5548' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [7] = \sq_figure[9] [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5588' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [7] = \sq_figure[11] [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5600' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [19] = \sq_figure[11] [19]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5682' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5673 [7] = \ps2_data_reg [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5596' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [15] = \sq_figure[11] [15]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5653' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5649 [2] = \ps2_data_reg [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5655' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5649 [4] = \ps2_data_reg [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5658' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5649 [7] = \ps2_data_reg [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5628' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5625 [1] = \ps2_data_reg [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5630' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5625 [3] = \ps2_data_reg [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5634' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5625 [7] = \ps2_data_reg [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5482' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5480 [0] = \ps2_cntr [0]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5769' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5079' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5076 [1] = \ps2_clk_buf [1]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5770' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5771' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5772' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5587' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [6] = \sq_figure[11] [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5540' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [19] = \sq_figure[8] [19]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5539' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [18] = \sq_figure[8] [18]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5583' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [2] = \sq_figure[11] [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5538' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [17] = \sq_figure[8] [17]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5537' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [16] = \sq_figure[8] [16]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5761' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5762' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5607' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5601 [4] = \ps2_data_reg_prev [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5605' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5601 [2] = \ps2_data_reg_prev [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5606' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5601 [3] = \ps2_data_reg_prev [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5603' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5601 [0] = \ps2_data_reg_prev [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5604' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5601 [1] = \ps2_data_reg_prev [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5706' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5697 [7] = \ps2_data_reg [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5702' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5697 [3] = \ps2_data_reg [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5700' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5697 [1] = \ps2_data_reg [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5699' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5697 [0] = \ps2_data_reg [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5678' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5673 [3] = \ps2_data_reg [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5677' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5673 [2] = \ps2_data_reg [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5675' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5673 [0] = \ps2_data_reg [0]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5763' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5764' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5765' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5766' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5767' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5768' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5535' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [14] = \sq_figure[8] [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5534' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [13] = \sq_figure[8] [13]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5737' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5738' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5739' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5740' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5741' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5582' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [1] = \sq_figure[11] [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5529' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [8] = \sq_figure[8] [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5528' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [7] = \sq_figure[8] [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5527' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [6] = \sq_figure[8] [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5595' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [14] = \sq_figure[11] [14]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5721' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5722' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5723' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5724' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5725' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5726' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5526' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [5] = \sq_figure[8] [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5525' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [4] = \sq_figure[8] [4]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5729' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5730' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5731' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5524' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [3] = \sq_figure[8] [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5549' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [8] = \sq_figure[9] [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5586' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [5] = \sq_figure[11] [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5585' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [4] = \sq_figure[11] [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5523' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [2] = \sq_figure[8] [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5522' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [1] = \sq_figure[8] [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5521' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [0] = \sq_figure[8] [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5439' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [7] = \c_col [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5438' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [6] = \c_col [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5437' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [5] = \c_col [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5436' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [4] = \c_col [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5435' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [3] = \c_col [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5434' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [2] = \c_col [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5433' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [1] = \c_col [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5441' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [9] = \c_col [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5440' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5430 [8] = \c_col [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6189' (?x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][1][1]$a$1899 [16] = $memory\sq_figure$rdmux[0][2][2]$a$1908 [16]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5316' (?x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][0][0]$b$1894 [16] = $memory\sq_figure$rdmux[0][2][2]$a$1908 [16]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$4895' (01?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][3][0]$a$1914 [12] = \sq_fig_y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6187' (0x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][1][1]$a$1899 [19] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5314' (0x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][0][0]$b$1894 [19] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6191' (1x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][1][1]$a$1899 [12] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5318' (1x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][0][0]$b$1894 [12] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7019' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [8] = $memrd$\sq_figure$example.v:202$155_DATA [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7015' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [4] = $memrd$\sq_figure$example.v:202$155_DATA [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7023' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [12] = $memrd$\sq_figure$example.v:202$155_DATA [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6044' (01?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][2][0]$b$1903 [18] = \sq_fig_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7021' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [10] = $memrd$\sq_figure$example.v:202$155_DATA [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6190' (?x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][1][1]$a$1899 [14] = $memory\sq_figure$rdmux[0][2][2]$a$1908 [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5317' (?x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][0][0]$b$1894 [14] = $memory\sq_figure$rdmux[0][2][2]$a$1908 [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6146' (01?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][2][0]$a$1902 [14] = \sq_fig_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7017' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [6] = $memrd$\sq_figure$example.v:202$155_DATA [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7025' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [14] = $memrd$\sq_figure$example.v:202$155_DATA [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6188' (?x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][1][1]$a$1899 [17] = $memory\sq_figure$rdmux[0][2][2]$a$1908 [17]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5315' (?x?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][0][0]$b$1894 [17] = $memory\sq_figure$rdmux[0][2][2]$a$1908 [17]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5964' (01?) in module `\top' with constant driver `$memory\sq_figure$rdmux[0][1][0]$a$1896 [17] = \sq_fig_y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7020' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [9] = $memrd$\sq_figure$example.v:202$155_DATA [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7016' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [5] = $memrd$\sq_figure$example.v:202$155_DATA [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7024' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [13] = $memrd$\sq_figure$example.v:202$155_DATA [13]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7022' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [11] = $memrd$\sq_figure$example.v:202$155_DATA [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7018' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [7] = $memrd$\sq_figure$example.v:202$155_DATA [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7026' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [15] = $memrd$\sq_figure$example.v:202$155_DATA [15]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6557' (01?) in module `\top' with constant driver `$procmux$946_Y [2] = $shiftx$example.v:202$156.buffer [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7710' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7711' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7712' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7713' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7714' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7715' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7716' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7717' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7708' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7709' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1110.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7620' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7621' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7622' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7623' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7624' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7625' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7626' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7627' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7618' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7619' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1099.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5292' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5283 [7] = \c_col [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5293' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5283 [8] = \c_col [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5260' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5253 [5] = \c_row [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5264' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5253 [9] = \c_row [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5554' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [13] = \sq_figure[9] [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5581' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [0] = \sq_figure[11] [0]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5817' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5732' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5733' in module `top'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7221' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7211' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5594' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [13] = \sq_figure[11] [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5409' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [6] = \c_row [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5410' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [7] = \c_row [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5407' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [4] = \c_row [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5408' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [5] = \c_row [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5405' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [2] = \c_row [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5406' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [3] = \c_row [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5404' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [1] = \c_row [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5411' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [8] = \c_row [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5412' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$5401 [9] = \c_row [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5599' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [18] = \sq_figure[11] [18]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7220' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5584' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [3] = \sq_figure[11] [3]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5742' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5743' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5744' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5597' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [16] = \sq_figure[11] [16]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5598' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [17] = \sq_figure[11] [17]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5589' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:309$29_DATA[19:0]$115 [8] = \sq_figure[11] [8]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5745' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5555' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [14] = \sq_figure[9] [14]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5746' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5556' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [15] = \sq_figure[9] [15]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5557' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [16] = \sq_figure[9] [16]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5558' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [17] = \sq_figure[9] [17]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7219' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7209' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5559' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [18] = \sq_figure[9] [18]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5560' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [19] = \sq_figure[9] [19]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5561' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [0] = \sq_figure[10] [0]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7437' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7447' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7457' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [9] = \c_hor [9]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7436' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7446' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7435' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7445' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7455' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [7] = \c_hor [7]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7434' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7444' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5562' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [1] = \sq_figure[10] [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7433' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7443' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7432' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7442' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5563' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [2] = \sq_figure[10] [2]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7431' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7441' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5564' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [3] = \sq_figure[10] [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5565' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [4] = \sq_figure[10] [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5566' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [5] = \sq_figure[10] [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5567' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [6] = \sq_figure[10] [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5568' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [7] = \sq_figure[10] [7]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7430' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7440' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5569' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [8] = \sq_figure[10] [8]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7429' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7439' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7428' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7438' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1185.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5574' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [13] = \sq_figure[10] [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5575' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [14] = \sq_figure[10] [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5576' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [15] = \sq_figure[10] [15]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5536' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:306$26_DATA[19:0]$106 [15] = \sq_figure[8] [15]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5578' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [17] = \sq_figure[10] [17]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5577' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [16] = \sq_figure[10] [16]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5579' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [18] = \sq_figure[10] [18]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5580' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:308$28_DATA[19:0]$112 [19] = \sq_figure[10] [19]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7417' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7427' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7416' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7415' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7414' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7413' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7412' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7422' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7411' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7410' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7409' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7419' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7408' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7418' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7377' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [9] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7387' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [9] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7376' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7386' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [8] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7375' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7385' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7374' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [6] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7384' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [6] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7373' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7383' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7372' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7382' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [4] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7371' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7381' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [3] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7370' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7380' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [2] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7369' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7379' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [1] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7368' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7378' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [0] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7388' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [0] = \sq_pos_x [0]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5818' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5819' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5820' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5821' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5822' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5747' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5823' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5734' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5735' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5736' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5748' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5824' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5749' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5750' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5751' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5727' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5728' in module `top'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7346' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7356' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = 1'1'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5752' in module `top'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7345' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7355' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7365' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [7] = \c_hor [7]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7344' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7354' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7364' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [6] = \c_hor [6]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5753' in module `top'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7343' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7353' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7363' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [5] = \c_hor [5]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7342' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7352' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7362' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [4] = \c_hor [4]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7341' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7351' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7340' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7350' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7339' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7349' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7338' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7348' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = 1'1'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5754' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5773' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5774' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5775' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5796' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5755' in module `top'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7347' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7357' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = 1'0'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5756' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5757' in module `top'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7317' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [9] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7327' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [9] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7316' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7326' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [8] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7315' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7325' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7314' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [6] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7324' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [6] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7313' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7323' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7312' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7322' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [4] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7311' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7321' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [3] = 1'1'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5758' in module `top'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7310' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7320' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [2] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7309' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7319' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [1] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7308' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6401_Y [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7318' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6402_Y [0] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7328' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [0] = \sq_pos_y [0]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5759' in module `top'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7198' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7291' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [7] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7299' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [7] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7307' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127_Y [7] = \timer_t [7]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7290' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7298' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [6] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7306' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127_Y [6] = \timer_t [6]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5760' in module `top'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7289' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7297' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [5] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7305' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127_Y [5] = \timer_t [5]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7288' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [4] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7296' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [4] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7304' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127_Y [4] = \timer_t [4]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7287' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7295' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [3] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7303' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127_Y [3] = \timer_t [3]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7286' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7294' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [2] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7285' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [1] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7293' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [1] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7301' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127_Y [1] = \timer_t [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7284' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5125_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7292' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1137.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5126_Y [0] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5541' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [0] = \sq_figure[9] [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7367' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [9] = \c_hor [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7278' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1265.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7277' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1265.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7276' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1265.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7275' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1265.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7274' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1265.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [0]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7248' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7258' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7268' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [9] = \sq_pos_x [9]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7247' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7257' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5542' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [1] = \sq_figure[9] [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7246' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7256' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7245' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7255' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7265' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [6] = \sq_pos_x [6]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7244' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7254' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7264' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [5] = \sq_pos_x [5]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7243' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7253' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7263' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [4] = \sq_pos_x [4]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7242' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7252' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7241' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7251' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7261' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] = \sq_pos_x [2]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7240' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7250' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7239' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7249' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7259' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [0] = \sq_pos_x [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5543' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [2] = \sq_figure[9] [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5544' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [3] = \sq_figure[9] [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5545' (?0) in module `\top' with constant driver `$0$memwr$\sq_figure$example.v:307$27_DATA[19:0]$109 [4] = \sq_figure[9] [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7228' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7197' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7227' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7226' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7225' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7224' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7223' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7222' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7218' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7217' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7216' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7196' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7195' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7194' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7193' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7192' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7191' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7190' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7189' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7188' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7187' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7186' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7185' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7184' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7183' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7181' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7179' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1246.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7162' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.$ternary$/usr/local/bin/../share/yosys/techmap.v:258$6546_Y [1] = \clk_div [1]'. Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$7173' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.$and$/usr/local/bin/../share/yosys/techmap.v:260$6547_Y [1] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7175' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.$xor$/usr/local/bin/../share/yosys/techmap.v:262$6548_Y [1] = \clk_div [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7161' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.$ternary$/usr/local/bin/../share/yosys/techmap.v:258$6546_Y [0] = \clk_div [0]'. Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$7172' (and_or_buffer) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.$and$/usr/local/bin/../share/yosys/techmap.v:260$6547_Y [0] = \clk_div [0]'. Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$7875' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.lcu.$and$/usr/local/bin/../share/yosys/techmap.v:212$7167_Y = 1'0'. Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7873' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:491:replace_alu$1245 [0] = \clk_div [0]'. Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7872' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:491:replace_alu$1245 [1] = $techmap$auto$alumacc.cc:474:replace_alu$1243.lcu.$and$/usr/local/bin/../share/yosys/techmap.v:221$7169_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7178' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.$xor$/usr/local/bin/../share/yosys/techmap.v:263$6549_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1243.lcu.$and$/usr/local/bin/../share/yosys/techmap.v:221$7169_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7176' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1243.$xor$/usr/local/bin/../share/yosys/techmap.v:263$6549_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1243.$xor$/usr/local/bin/../share/yosys/techmap.v:262$6548_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7852' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7862' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7853' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7860' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7861' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7871' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7858' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7859' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7856' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7866' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7857' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7854' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7864' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7855' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1190.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7472' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7482' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7473' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7470' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7480' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7471' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7481' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7476' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7477' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7487' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7474' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7475' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7468' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7478' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7469' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7479' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7762' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7763' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7770' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7771' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7768' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7778' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7769' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7779' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7766' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7767' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7777' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7764' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7765' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1211.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7215' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7680' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7681' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7691' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7682' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7683' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7693' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7684' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7685' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7686' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7687' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7697' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7678' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7679' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4897_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7689' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1153.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7214' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6316' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6320' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6315' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6319' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6314' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6318' in module `top'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7213' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1254.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6313' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6317' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6244' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6252' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6243' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6251' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6242' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6250' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6241' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6249' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6240' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6248' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6239' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6247' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6238' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6246' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6237' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6245' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6236' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6235' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6234' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6233' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6232' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6231' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6230' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6229' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6228' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6227' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6226' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6198' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6200' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6201' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6203' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6204' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6225' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6181' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6182' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6184' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6185' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6186' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6192' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6166' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6168' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6169' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6171' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6172' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6173' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6154' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6155' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6157' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6158' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6159' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6160' in module `top'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6899' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [0] = \c_hor [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6900' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [1] = \c_hor [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6830' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [1] = \c_hor [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6901' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [2] = \c_hor [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6831' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [2] = \c_hor [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6902' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [3] = \c_hor [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6832' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [3] = \c_hor [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6903' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [4] = \c_hor [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6833' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [4] = \c_hor [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6904' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [5] = \c_hor [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6834' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [5] = \c_hor [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6905' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [6] = \c_hor [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6835' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [6] = \c_hor [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6906' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [7] = \c_hor [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6836' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [7] = \c_hor [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6907' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [8] = \c_hor [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6837' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [8] = \c_hor [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6908' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [9] = \c_hor [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6838' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [9] = \c_hor [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6839' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [0] = \sq_pos_y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6840' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [1] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6841' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [2] = \sq_pos_y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6842' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [3] = \sq_pos_y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6843' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [4] = \sq_pos_y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6844' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [5] = \sq_pos_y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6845' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [6] = \sq_pos_y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6846' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [7] = \sq_pos_y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6847' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [8] = \sq_pos_y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6848' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [9] = \sq_pos_y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6859' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [0] = \c_ver [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6860' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [1] = \c_ver [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6861' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [2] = \c_ver [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6862' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [3] = \c_ver [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6863' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [4] = \c_ver [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6864' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [5] = \c_ver [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6865' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [6] = \c_ver [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6866' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [7] = \c_ver [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6867' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [8] = \c_ver [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6868' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [9] = \c_ver [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6870' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [1] = \c_ver [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6871' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [2] = \c_ver [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6872' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [3] = \c_ver [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6873' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [4] = \c_ver [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6874' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [5] = \c_ver [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6875' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [6] = \c_ver [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6876' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [7] = \c_ver [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6877' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [8] = \c_ver [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6878' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [9] = \c_ver [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6880' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [1] = \sq_pos_y [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6881' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [2] = \sq_pos_y [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6882' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [3] = \sq_pos_y [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6883' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [4] = \sq_pos_y [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6884' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [5] = \sq_pos_y [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6885' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [6] = \sq_pos_y [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6886' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [7] = \sq_pos_y [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6887' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [8] = \sq_pos_y [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6888' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [9] = \sq_pos_y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6919' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [0] = \sq_pos_x [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6920' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [1] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6921' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [2] = \sq_pos_x [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6922' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [3] = \sq_pos_x [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6923' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [4] = \sq_pos_x [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6924' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [5] = \sq_pos_x [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6925' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [6] = \sq_pos_x [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6926' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [7] = \sq_pos_x [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6927' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [8] = \sq_pos_x [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6928' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6561_Y [9] = \sq_pos_x [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6930' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [1] = \sq_pos_x [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6931' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [2] = \sq_pos_x [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6932' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [3] = \sq_pos_x [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6933' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [4] = \sq_pos_x [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6934' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [5] = \sq_pos_x [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6935' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [6] = \sq_pos_x [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6936' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [7] = \sq_pos_x [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6937' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [8] = \sq_pos_x [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6938' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [9] = \sq_pos_x [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6943' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1237.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6555_Y [0] = \ps2_cntr [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6944' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1237.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6555_Y [1] = \ps2_cntr [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6945' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1237.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6555_Y [2] = \ps2_cntr [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6946' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1237.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6555_Y [3] = \ps2_cntr [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6948' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1237.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6556_Y [1] = \ps2_cntr [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6949' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1237.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6556_Y [2] = \ps2_cntr [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$6950' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1237.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6556_Y [3] = \ps2_cntr [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7027' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [16] = $memrd$\sq_figure$example.v:202$155_DATA [16]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7028' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [17] = $memrd$\sq_figure$example.v:202$155_DATA [17]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7029' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [18] = $memrd$\sq_figure$example.v:202$155_DATA [18]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7030' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$1\buffer[19:0] [19] = $memrd$\sq_figure$example.v:202$155_DATA [19]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7043' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [12] = $memrd$\sq_figure$example.v:202$155_DATA [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7044' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [13] = $memrd$\sq_figure$example.v:202$155_DATA [13]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7045' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [14] = $memrd$\sq_figure$example.v:202$155_DATA [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7046' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [15] = $memrd$\sq_figure$example.v:202$155_DATA [15]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7047' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [16] = $memrd$\sq_figure$example.v:202$155_DATA [16]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7048' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [17] = $memrd$\sq_figure$example.v:202$155_DATA [17]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7049' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [18] = $memrd$\sq_figure$example.v:202$155_DATA [18]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7050' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$4\buffer[19:0] [19] = $memrd$\sq_figure$example.v:202$155_DATA [19]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6987' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$11\buffer[19:0] [14] = $memrd$\sq_figure$example.v:202$155_DATA [16]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6988' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$11\buffer[19:0] [15] = $memrd$\sq_figure$example.v:202$155_DATA [17]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6989' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$11\buffer[19:0] [16] = $memrd$\sq_figure$example.v:202$155_DATA [18]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6990' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$11\buffer[19:0] [17] = $memrd$\sq_figure$example.v:202$155_DATA [19]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7009' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$10\buffer[19:0] [18] = $memrd$\sq_figure$example.v:202$155_DATA [18]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7010' (?x?) in module `\top' with constant driver `$techmap$shiftx$example.v:202$156.$10\buffer[19:0] [19] = $memrd$\sq_figure$example.v:202$155_DATA [19]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$6970' (?x?) in module `\top' with constant driver `$shiftx$example.v:202$156.buffer [19] = $memrd$\sq_figure$example.v:202$155_DATA [19]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7072' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [0] = \arr_timer [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7073' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [1] = \arr_timer [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7074' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [2] = \arr_timer [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7075' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [3] = \arr_timer [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7076' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [4] = \arr_timer [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7077' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [5] = \arr_timer [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7078' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [6] = \arr_timer [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7079' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [7] = \arr_timer [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7080' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [8] = \arr_timer [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7081' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [9] = \arr_timer [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7082' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [10] = \arr_timer [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7083' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [11] = \arr_timer [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7084' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [12] = \arr_timer [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7085' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [13] = \arr_timer [13]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7086' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [14] = \arr_timer [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7087' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [15] = \arr_timer [15]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7088' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [16] = \arr_timer [16]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7089' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [17] = \arr_timer [17]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7090' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [18] = \arr_timer [18]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7091' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [19] = \arr_timer [19]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7092' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6552_Y [20] = \arr_timer [20]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7094' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [1] = \arr_timer [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7095' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [2] = \arr_timer [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7096' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [3] = \arr_timer [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7097' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [4] = \arr_timer [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7098' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [5] = \arr_timer [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7099' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [6] = \arr_timer [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7100' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [7] = \arr_timer [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7101' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [8] = \arr_timer [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7102' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [9] = \arr_timer [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7103' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [10] = \arr_timer [10]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7104' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [11] = \arr_timer [11]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7105' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [12] = \arr_timer [12]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7106' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [13] = \arr_timer [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7107' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [14] = \arr_timer [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7108' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [15] = \arr_timer [15]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7109' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [16] = \arr_timer [16]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7110' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [17] = \arr_timer [17]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7111' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [18] = \arr_timer [18]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7112' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [19] = \arr_timer [19]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7113' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1240.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6553_Y [20] = \arr_timer [20]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7119' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1262.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7120' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1262.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7121' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1262.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7122' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1262.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7123' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1262.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5346_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [4]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7129' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [0] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7130' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [1] = 1'0'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7131' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [2] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7132' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [3] = 1'0'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7133' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [4] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7134' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7135' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [6] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7136' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7137' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [8] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7138' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [9] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7139' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7140' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [1] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7141' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7142' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7143' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7144' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7145' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [6] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7146' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7147' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7148' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [9] = 1'1'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7150' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [1] = \sq_pos_x [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7152' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [3] = \sq_pos_x [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7498' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7499' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7500' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7501' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7502' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7503' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7504' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7505' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7506' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7507' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1169.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1169.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7528' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [0] = \sq_pos_x [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7529' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [1] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7530' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [2] = \sq_pos_x [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7531' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [3] = \sq_pos_x [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7532' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [4] = \sq_pos_x [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7533' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [5] = \sq_pos_x [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7534' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [6] = \sq_pos_x [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7535' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [7] = \sq_pos_x [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7536' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [8] = \sq_pos_x [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7537' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [9] = \sq_pos_x [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7538' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [0] = \sq_pos_x [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7540' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [2] = \sq_pos_x [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7542' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [4] = \sq_pos_x [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7543' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [5] = \sq_pos_x [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7544' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [6] = \sq_pos_x [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7545' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [7] = \sq_pos_x [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7546' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [8] = \sq_pos_x [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7547' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [9] = \sq_pos_x [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7558' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7559' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7560' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7561' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7562' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7563' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7564' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7565' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7566' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7567' (??1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1164.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1164.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7588' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [0] = \sq_pos_y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7589' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [1] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7590' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [2] = \sq_pos_y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7591' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [3] = \sq_pos_y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7592' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [4] = \sq_pos_y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7593' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [5] = \sq_pos_y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7594' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [6] = \sq_pos_y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7595' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [7] = \sq_pos_y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7596' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [8] = \sq_pos_y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7597' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4974_Y [9] = \sq_pos_y [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7598' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [0] = \sq_pos_y [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7600' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [2] = \sq_pos_y [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7602' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [4] = \sq_pos_y [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7603' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [5] = \sq_pos_y [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7604' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [6] = \sq_pos_y [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7605' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [7] = \sq_pos_y [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7606' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [8] = \sq_pos_y [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7607' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [9] = \sq_pos_y [9]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7658' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7648' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [0] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7659' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [1] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7649' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [1] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7639' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [1] = \sq_pos_y [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7660' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7650' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [2] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7661' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7651' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [3] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7641' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [3] = \sq_pos_y [3]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7662' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7652' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [4] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7663' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7653' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7664' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [6] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7654' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [6] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7665' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7655' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7666' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7656' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [8] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7667' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5342_Y [9] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7657' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1277.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5343_Y [9] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7736' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [0] = \timer_t [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7737' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [1] = \timer_t [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7729' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [1] = \timer_t [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7738' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [2] = \timer_t [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7730' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [2] = \timer_t [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7739' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [3] = \timer_t [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7731' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [3] = \timer_t [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7740' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [4] = \timer_t [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7732' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [4] = \timer_t [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7741' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [5] = \timer_t [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7733' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [5] = \timer_t [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7742' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [6] = \timer_t [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7734' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [6] = \timer_t [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7743' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6703_Y [7] = \timer_t [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7735' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [7] = \timer_t [7]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7782' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7783' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7784' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] = 1'0'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7785' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] = 1'0'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7786' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7787' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7788' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7789' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7790' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7791' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7792' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7793' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7794' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7795' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7796' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7797' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7798' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7799' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7800' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7801' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7804' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] = \c_ver [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7805' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] = \c_ver [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7811' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1206.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [9] = \c_ver [9]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7812' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = 1'0'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7813' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7814' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7815' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7816' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] = 1'0'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7817' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7818' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7819' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7] = 1'0'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7820' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7821' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7822' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7823' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7824' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7825' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7826' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [4] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7827' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7828' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [6] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7829' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [7] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7830' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [8] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$7831' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4977_Y [9] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7832' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [0] = \c_hor [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7836' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [4] = \c_hor [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7839' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [7] = \c_hor [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7841' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [9] = \c_hor [9]'. 2.14.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7579' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6890'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7579' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7581' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6892'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7581' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7583' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6894'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7583' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7585' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6896'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7585' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7578' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6889'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7578' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7580' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6891'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7580' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7582' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6893'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7582' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7584' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6895'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7584' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7640' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7330'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [2] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7640' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6850' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7753'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6850' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7638' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$6879'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7638' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7401' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7461'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7401' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7755' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6852'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7755' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7629' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7280'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7629' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6826' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7465'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6826' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6822' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7461'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6822' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6821' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7460'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6821' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7675' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6896'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7675' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7644' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7334'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7644' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7404' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6825'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7404' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7402' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6823'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7402' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7406' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6827'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7406' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7260' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7539'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7260' from module `\top'. Cell `$auto$simplemap.cc:420:simplemap_dff$6569' is identical to cell `$auto$simplemap.cc:420:simplemap_dff$6570'. Redirecting output \Q: \vga_b_r [0] = \vga_b_r [1] Removing $_DFF_P_ cell `$auto$simplemap.cc:420:simplemap_dff$6569' from module `\top'. Cell `$auto$simplemap.cc:420:simplemap_dff$6566' is identical to cell `$auto$simplemap.cc:420:simplemap_dff$6567'. Redirecting output \Q: \vga_r_r [0] = \vga_r_r [1] Removing $_DFF_P_ cell `$auto$simplemap.cc:420:simplemap_dff$6566' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6828' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7851'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6828' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7200' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6910'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7200' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7201' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6911'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7201' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7203' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6913'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7203' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7599' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7329'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7599' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7202' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6912'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7202' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6858' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7761'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6858' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7601' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7331'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7601' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7358' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$6829'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7358' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7466' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6827'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7466' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7676' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6897'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7676' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7673' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6894'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7673' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7199' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6909'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7199' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7459' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6820'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7459' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7449' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7359'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7449' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7458' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6819'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7458' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7448' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$6829'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7448' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7518' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6909'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7518' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7208' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6918'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7208' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7207' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6917'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7207' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7206' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6916'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7206' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7238' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6898'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7238' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7266' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7156'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [7] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7266' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7462' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6823'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7462' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7205' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6915'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7205' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7586' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6897'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7586' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7642' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7332'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [4] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7642' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7399' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6820'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7399' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7450' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7360'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7450' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7647' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7337'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [9] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7647' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7758' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6855'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7758' from module `\top'. Cell `$auto$simplemap.cc:277:simplemap_mux$5937' is identical to cell `$auto$simplemap.cc:277:simplemap_mux$5961'. Redirecting output \Y: $memory\sq_figure$rdmux[0][2][2]$a$1908 [17] = $memory\sq_figure$rdmux[0][2][1]$b$1906 [19] Removing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5937' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7835' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7361'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7835' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7834' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7360'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7834' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7833' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7359'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7833' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5681' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5705'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5673 [6] = $auto$simplemap.cc:250:simplemap_eqne$5697 [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5681' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5680' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5704'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5673 [5] = $auto$simplemap.cc:250:simplemap_eqne$5697 [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5680' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5679' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5703'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5673 [4] = $auto$simplemap.cc:250:simplemap_eqne$5697 [4] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5679' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5657' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5705'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5649 [6] = $auto$simplemap.cc:250:simplemap_eqne$5697 [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5657' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5656' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5704'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5649 [5] = $auto$simplemap.cc:250:simplemap_eqne$5697 [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5656' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7672' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6893'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7672' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7670' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6891'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7670' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5652' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5676'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5649 [1] = $auto$simplemap.cc:250:simplemap_eqne$5673 [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5652' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7233' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6893'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7233' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5633' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5705'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5625 [6] = $auto$simplemap.cc:250:simplemap_eqne$5697 [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5633' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5632' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5704'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5625 [5] = $auto$simplemap.cc:250:simplemap_eqne$5697 [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5632' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5631' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5703'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5625 [4] = $auto$simplemap.cc:250:simplemap_eqne$5697 [4] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5631' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5629' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5701'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5625 [2] = $auto$simplemap.cc:250:simplemap_eqne$5697 [2] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5629' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5627' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5651'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5625 [0] = $auto$simplemap.cc:250:simplemap_eqne$5649 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5627' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7844' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7460'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7844' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7842' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6819'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7842' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7843' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6820'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7843' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7837' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7453'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7837' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7838' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7454'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7838' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7759' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6856'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7759' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7718' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7114'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7718' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7850' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6827'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7850' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7262' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7541'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7262' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7403' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6824'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7403' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7847' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6824'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7847' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7234' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6894'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7234' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7520' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6911'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7520' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7668' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6889'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7668' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7669' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6890'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7669' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7674' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6895'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7674' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7752' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6849'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7752' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7754' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6851'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7754' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7392' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7153'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [4] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7392' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7391' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7541'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7391' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7389' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7539'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1251.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4975_Y [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7389' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7632' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7283'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7632' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7757' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6854'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7757' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7394' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7155'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7394' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7398' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6819'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7398' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7230' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6890'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7230' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7521' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6912'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7521' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7464' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6825'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7464' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7848' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6825'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7848' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7846' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6823'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7846' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7845' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7461'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7845' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7149' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$6929'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7149' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7802' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$6869'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1206.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6562_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7802' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7405' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7465'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7405' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7728' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7300'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1222.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6704_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1137.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5127_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7728' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7519' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6910'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7519' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7451' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7361'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7451' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7154' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7393'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7154' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7118' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7722'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7118' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7671' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6892'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7671' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7158' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7397'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [9] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7158' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5285' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5432'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5283 [0] = $auto$simplemap.cc:250:simplemap_eqne$5430 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5285' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$5255' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$5403'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$5253 [0] = $auto$simplemap.cc:250:simplemap_eqne$5401 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$5255' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5243' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5449'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5238 [4] = $auto$simplemap.cc:127:simplemap_reduce$5444 [4] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5243' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5242' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5448'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5238 [3] = $auto$simplemap.cc:127:simplemap_reduce$5444 [3] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5242' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5241' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5447'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5238 [2] = $auto$simplemap.cc:127:simplemap_reduce$5444 [2] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5241' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5240' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5446'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5238 [1] = $auto$simplemap.cc:127:simplemap_reduce$5444 [1] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5240' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5229' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5420'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5224 [4] = $auto$simplemap.cc:127:simplemap_reduce$5415 [4] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5229' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5228' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5419'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5224 [3] = $auto$simplemap.cc:127:simplemap_reduce$5415 [3] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5228' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5227' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5418'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5224 [2] = $auto$simplemap.cc:127:simplemap_reduce$5415 [2] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5227' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5226' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5417'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5224 [1] = $auto$simplemap.cc:127:simplemap_reduce$5415 [1] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5226' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7236' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6896'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7236' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7526' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6917'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7526' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7525' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6916'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7525' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7524' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6915'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7524' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7281' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7630'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7281' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7115' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7719'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7115' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7116' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7720'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7116' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7117' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7721'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1262.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7117' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7756' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6853'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7756' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7463' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6824'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1228.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7463' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7395' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7156'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [7] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7395' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7407' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7851'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7407' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7229' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6889'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7229' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7698' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7124'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1110.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7698' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7702' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7128'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1110.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [4] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7702' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7467' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7851'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7467' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7645' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7335'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [7] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7645' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7643' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7333'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7643' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7485' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7425'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [7] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7485' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7527' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6918'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7527' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7151' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7390'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [2] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7151' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7204' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6914'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1246.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7204' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7587' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6898'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1259.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7587' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7232' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6892'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7232' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7677' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6898'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1153.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [9] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [9] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7677' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7628' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7279'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [0] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7628' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7396' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7267'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1271.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [8] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7396' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7336' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7646'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1268.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$6403_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1277.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [8] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7336' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7282' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7631'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1265.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$5345_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [3] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7282' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7237' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6897'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7237' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7523' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6914'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [5] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7523' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7456' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7840'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1185.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [8] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7456' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7426' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7486'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [8] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7426' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6857' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7760'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1225.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1211.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4976_Y [8] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6857' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7235' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6895'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [6] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7235' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7522' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6913'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1251.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1234.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [4] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7522' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7157' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7267'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1274.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5344_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1148.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [8] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7157' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7366' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7840'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1126.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1201.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [8] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7366' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7127' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7701'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1262.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7127' from module `\top'. Cell `$auto$simplemap.cc:277:simplemap_mux$5939' is identical to cell `$auto$simplemap.cc:277:simplemap_mux$5962'. Redirecting output \Y: $memory\sq_figure$rdmux[0][2][2]$a$1908 [14] = $memory\sq_figure$rdmux[0][2][1]$b$1906 [18] Removing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$5939' from module `\top'. Cell `$auto$simplemap.cc:420:simplemap_dff$6568' is identical to cell `$auto$simplemap.cc:420:simplemap_dff$6567'. Redirecting output \Q: \vga_r_r [2] = \vga_r_r [1] Removing $_DFF_P_ cell `$auto$simplemap.cc:420:simplemap_dff$6568' from module `\top'. Cell `$auto$simplemap.cc:420:simplemap_dff$6571' is identical to cell `$auto$simplemap.cc:420:simplemap_dff$6570'. Redirecting output \Q: \vga_b_r [2] = \vga_b_r [1] Removing $_DFF_P_ cell `$auto$simplemap.cc:420:simplemap_dff$6571' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7400' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7460'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7400' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7849' is identical to cell `$auto$simplemap.cc:37:simplemap_not$7465'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4896_Y [7] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7849' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7231' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6891'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1254.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$4973_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1231.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$6560_Y [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7231' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7612' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7273'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1099.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [4] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [4] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7612' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5689' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5713'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5685 [3] = $auto$simplemap.cc:127:simplemap_reduce$5709 [3] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5689' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5688' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5712'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5685 [2] = $auto$simplemap.cc:127:simplemap_reduce$5709 [2] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5688' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5665' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5713'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5661 [3] = $auto$simplemap.cc:127:simplemap_reduce$5709 [3] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5665' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7424' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7484'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7424' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5641' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5713'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5637 [3] = $auto$simplemap.cc:127:simplemap_reduce$5709 [3] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5641' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5640' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5712'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5637 [2] = $auto$simplemap.cc:127:simplemap_reduce$5709 [2] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5640' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5639' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5711'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5637 [1] = $auto$simplemap.cc:127:simplemap_reduce$5709 [1] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5639' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7609' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7270'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1099.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7609' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7699' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7125'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1110.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [1] = $techmap$auto$alumacc.cc:474:replace_alu$1262.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7699' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7867' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7423'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7867' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7868' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7484'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [6] = $techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [6] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7868' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7271' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7610'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1265.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1099.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7271' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7483' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7423'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [5] = $techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7483' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7126' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7700'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1262.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [2] = $techmap$auto$alumacc.cc:474:replace_alu$1110.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [2] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7126' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5246' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5452'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5244 [1] = $auto$simplemap.cc:127:simplemap_reduce$5450 [1] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5246' from module `\top'. Cell `$auto$simplemap.cc:177:logic_reduce$5232' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5423'. Redirecting output \Y: $auto$simplemap.cc:168:logic_reduce$5230 [1] = $auto$simplemap.cc:127:simplemap_reduce$5421 [1] Removing $_OR_ cell `$auto$simplemap.cc:177:logic_reduce$5232' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7608' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7269'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1099.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7608' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7611' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7272'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1099.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4978_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1265.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$5347_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7611' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7421' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7865'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [3] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [3] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7421' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7425' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7869'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1121.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [7] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [7] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7425' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$7486' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$7870'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$1174.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [8] = $techmap$auto$alumacc.cc:474:replace_alu$1190.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$4898_Y [8] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$7486' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5692' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5716'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5690 [1] = $auto$simplemap.cc:127:simplemap_reduce$5714 [1] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5692' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$5644' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$5716'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$5642 [1] = $auto$simplemap.cc:127:simplemap_reduce$5714 [1] Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$5644' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$4984' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$6727'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$4981 [2] = $auto$simplemap.cc:127:simplemap_reduce$6724 [2] Removing $_AND_ cell `$auto$simplemap.cc:136:simplemap_reduce$4984' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$4983' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$6726'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$4981 [1] = $auto$simplemap.cc:127:simplemap_reduce$6724 [1] Removing $_AND_ cell `$auto$simplemap.cc:136:simplemap_reduce$4983' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$4982' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$6725'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$4981 [0] = $auto$simplemap.cc:127:simplemap_reduce$6724 [0] Removing $_AND_ cell `$auto$simplemap.cc:136:simplemap_reduce$4982' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$4988' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$6731'. Redirecting output \Y: $auto$simplemap.cc:127:simplemap_reduce$4987 [0] = $auto$simplemap.cc:127:simplemap_reduce$6730 [0] Removing $_AND_ cell `$auto$simplemap.cc:136:simplemap_reduce$4988' from module `\top'. Removed a total of 198 cells. 2.14.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$5672'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$5648'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7210'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$5696'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7454'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7453'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7452'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$5624'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1225.slice[9].carry'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7420'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7397'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7393'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7390'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1231.slice[9].carry'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$5720'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1228.slice[9].carry'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7337'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7335'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7334'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7333'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7332'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7331'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7330'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7329'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7267'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1234.slice[9].carry'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$5494'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1237.slice[3].carry'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7182'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7180'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1262.slice[4].carry'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1240.slice[20].carry'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1274.slice[9].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1246.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1254.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1148.slice[9].adder'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1265.slice[4].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1137.slice[7].adder'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1268.slice[9].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1126.slice[9].adder'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1271.slice[9].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1121.slice[9].adder'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$5085'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1185.slice[9].adder'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7212'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[0].adder'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6236'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6235'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[1].adder'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6234'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1174.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1169.slice[9].adder'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1251.slice[9].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1164.slice[9].adder'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1259.slice[9].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1099.slice[0].adder'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1277.slice[9].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1153.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1110.slice[0].adder'. removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$6672'. removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$6673'. removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$6674'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$1222.slice[7].carry'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1211.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1206.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1201.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[0].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$1190.slice[9].adder'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$6869'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$6879'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$6929'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$6939'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$6940'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$6941'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$6942'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$6947'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6952'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6953'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6954'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6955'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6956'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6957'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6958'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6959'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6960'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6961'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6962'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6963'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6964'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6965'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6966'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6967'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6968'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6969'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6975'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6976'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6977'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6978'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6979'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6980'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6981'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6982'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6983'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6984'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6985'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6986'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6993'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6994'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6995'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6996'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6997'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6998'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$6999'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7000'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7001'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7002'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7003'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7004'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7005'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7006'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7007'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7008'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7039'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7040'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7041'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$7042'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7051'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7052'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7053'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7054'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7055'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7056'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7057'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7058'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7059'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7060'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7061'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7062'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7063'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7064'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7065'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7066'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7067'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7068'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7069'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7070'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7071'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7093'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7153'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7155'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7156'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7159'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7160'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7508'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7509'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7510'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7511'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7512'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7513'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7514'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7515'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7516'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7517'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7539'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7541'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7568'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7569'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7570'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7571'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7572'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7573'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7574'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7575'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7576'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7577'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7646'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7744'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7745'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7746'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7747'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7748'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7749'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7750'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$7751'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7803'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7806'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7807'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7808'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7809'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$7810'. removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$7874'. removing unused non-port wire \ps2_clk_pos. removed 597 unused temporary wires. Removed 340 unused cells and 615 unused wires. 2.14.6. Rerunning OPT passes. (Removed registers in this run.) 2.14.7. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1121.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$1121.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1126.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1137.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1148.slice[0].carry: CO=\sq_pos_x [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1153.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1174.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$1121.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1190.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$1121.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1201.slice[0].carry: CO=\c_hor [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1206.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1211.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1222.slice[0].carry: CO=\timer_t [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1225.slice[0].carry: CO=\c_hor [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1228.slice[0].carry: CO=\c_ver [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1231.slice[0].carry: CO=\sq_pos_y [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1234.slice[0].carry: CO=\sq_pos_x [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1237.slice[0].carry: CO=\ps2_cntr [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1240.slice[0].carry: CO=\arr_timer [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1246.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$1246.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1251.slice[0].carry: CO=1'0 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1254.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$1153.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1259.slice[0].carry: CO=1'0 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1268.slice[0].carry: CO=\sq_pos_y [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1271.slice[0].carry: CO=\sq_pos_x [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1274.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1277.slice[0].carry: CO=1'1 Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1222.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1225.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1228.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1231.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1234.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1237.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1240.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1251.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1259.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1268.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1271.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1274.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1277.slice[1].adder back to logic. 2.14.8. Executing OPT_EXPR pass (perform const folding). Setting undriven signal in top to undef: \ps2_dat_r [9] Setting undriven signal in top to undef: \ps2_dat_r [10] Setting undriven signal in top to undef: \ps2_dat_r [8] Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8086' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8087' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8095' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8094 [0] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8088' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8089' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8100' (??0) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8099 [0] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8090' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8091' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8092' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8093' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8085 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8098' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8094 [3] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8101' (??0) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8099 [1] = $auto$simplemap.cc:309:simplemap_lut$8094 [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8103' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8102 = $auto$simplemap.cc:309:simplemap_lut$8094 [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8105' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8106' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8114' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8113 [0] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8107' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8108' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8119' (??0) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8118 [0] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8109' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8110' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8111' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8112' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8104 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8117' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8113 [3] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8120' (??0) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8118 [1] = $auto$simplemap.cc:309:simplemap_lut$8113 [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8122' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8121 = $auto$simplemap.cc:309:simplemap_lut$8113 [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7975' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7974' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7982' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7980 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7979' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7978' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7984' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7980 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7995' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7976' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7977' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7983' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7980 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7973' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7972' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7971 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7981' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7980 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7986' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7985 [0] = \ps2_cntr [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7992' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7996' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7993' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7997' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7994' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7991' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7959' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7960' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7965' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7961 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7958' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7957' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7964' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7961 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7954' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7953' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7962' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7961 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7956' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7955' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7952 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7963' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7961 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7967' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7966 [0] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7878' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7998' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7990 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8000' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7999 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8003' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7999 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8002' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7999 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8001' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7999 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8005' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8004 [0] = \arr_timer [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8010' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8011' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8012' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8013' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8014' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8015' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8016' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8017' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8009 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8020' (101) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8018 [1] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8019' (011) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8018 [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8021' (101) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8018 [2] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8022' (011) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8018 [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8025' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8023 [1] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8027' (??0) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8026 = $auto$simplemap.cc:309:simplemap_lut$8023 [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8029' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8030' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8031' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8032' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8033' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8035' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8034' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7877' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7879' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8036' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8028 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8038' (011) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8037 [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8039' (101) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8037 [1] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8040' (101) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8037 [2] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8041' (011) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8037 [3] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8044' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8042 [1] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8046' (??0) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8045 = $auto$simplemap.cc:309:simplemap_lut$8042 [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8048' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8050' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8049' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7880' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7881' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8051' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8052' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8053' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8054' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8055' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8047 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8057' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8056 [0] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8060' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8056 [3] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8062' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8061 [0] = $auto$simplemap.cc:309:simplemap_lut$8056 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8063' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8061 [1] = \sq_pos_y [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8067' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8068' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8069' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7883' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7884' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7889' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7885 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7882' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7876 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7888' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7885 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7887' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7885 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7886' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7885 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7891' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7890 [0] = \timer_t [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8070' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8071' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8072' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8073' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8074' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8066 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8076' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8075 [0] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8079' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8075 [3] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8081' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8080 [0] = $auto$simplemap.cc:309:simplemap_lut$8075 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8082' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8080 [1] = \sq_pos_x [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7903' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7902' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7908' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7904 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7901' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7900' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7907' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7904 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7899' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7898' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7906' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7904 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7897' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7896' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7895 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7905' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7904 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7910' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7909 [0] = \c_hor [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7922' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7921' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7927' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7923 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7920' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7919' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7926' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7923 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7918' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7917' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7925' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7923 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7915' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7916' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7914 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7924' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7923 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7929' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7928 [0] = \c_ver [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7941' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7940' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7946' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7942 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7939' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7938' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7945' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7942 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7937' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7936' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7944' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7942 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7935' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7934' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7933 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7943' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7942 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$7948' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$7947 [0] = \sq_pos_y [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7719' (double_invert) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$1110.BB [1] = \sq_pos_x [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7280' (double_invert) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$1099.BB [1] = \sq_pos_y [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7489' (double_invert) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$1169.BB [1] = \sq_pos_x [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7549' (double_invert) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$1164.BB [1] = \sq_pos_y [1]'. 2.14.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8043' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8058'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8042 [0] = $auto$simplemap.cc:309:simplemap_lut$8056 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8043' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8078' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8077'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8075 [2] = $auto$simplemap.cc:309:simplemap_lut$8075 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8078' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$7968' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8077'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$7966 [1] = $auto$simplemap.cc:309:simplemap_lut$8075 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$7968' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8096' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8077'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8094 [1] = $auto$simplemap.cc:309:simplemap_lut$8075 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8096' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$7949' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8058'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$7947 [1] = $auto$simplemap.cc:309:simplemap_lut$8056 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$7949' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8024' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8077'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8023 [0] = $auto$simplemap.cc:309:simplemap_lut$8075 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8024' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8115' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8058'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8113 [1] = $auto$simplemap.cc:309:simplemap_lut$8056 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8115' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8097' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8077'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8094 [2] = $auto$simplemap.cc:309:simplemap_lut$8075 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8097' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8116' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8058'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8113 [2] = $auto$simplemap.cc:309:simplemap_lut$8056 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8116' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6890' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8058'. Redirecting output \Y: $auto$alumacc.cc:474:replace_alu$1153.BB [1] = $auto$simplemap.cc:309:simplemap_lut$8056 [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6890' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6910' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8077'. Redirecting output \Y: $auto$alumacc.cc:474:replace_alu$1246.BB [1] = $auto$simplemap.cc:309:simplemap_lut$8075 [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6910' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$7930' is identical to cell `$auto$simplemap.cc:37:simplemap_not$6820'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$7928 [1] = $auto$alumacc.cc:474:replace_alu$1121.BB [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$7930' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8059' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8058'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8056 [2] = $auto$simplemap.cc:309:simplemap_lut$8056 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8059' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$7753' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$7911'. Redirecting output \Y: $auto$alumacc.cc:474:replace_alu$1211.BB [1] = $auto$simplemap.cc:309:simplemap_lut$7909 [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$7753' from module `\top'. Removed a total of 14 cells. 2.14.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removed 47 unused temporary wires. Removed 340 unused cells and 662 unused wires. 2.14.12. Rerunning OPT passes. (Removed registers in this run.) 2.14.13. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1126.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1137.slice[1].carry: CO=\timer_t [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1153.slice[1].carry: CO=\d_sq_pos_y [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1206.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1211.slice[1].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1251.slice[1].carry: CO=\sq_pos_x [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1259.slice[1].carry: CO=\sq_pos_y [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1274.slice[1].carry: CO=\sq_pos_x [1] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1277.slice[1].carry: CO=\sq_pos_y [1] Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1251.slice[2].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1259.slice[2].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1274.slice[2].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$1277.slice[2].adder back to logic. 2.14.14. Executing OPT_EXPR pass (perform const folding). Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8168' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8169' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8174' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8170 [3] = \sq_pos_x [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8166' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8167' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8177' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8175 [1] = \sq_pos_x [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8162' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8163' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8171' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8170 [0] = \sq_pos_x [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8164' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8165' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8161 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8176' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8175 [0] = $auto$simplemap.cc:309:simplemap_lut$8170 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8188' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8187' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8193' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8189 [3] = \sq_pos_y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8186' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8185' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8196' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8194 [1] = \sq_pos_y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8184' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8183' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8182' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8181' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8180 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8190' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8189 [0] = \sq_pos_y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8195' (??1) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8194 [0] = $auto$simplemap.cc:309:simplemap_lut$8189 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8146' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8148' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8147' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8150' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8149' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8144' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8143' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8152' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8151 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8145' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8142 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8131' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8130' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8136' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8132 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8129' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8128' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8135' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8132 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8127' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8126' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8134' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8132 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8125' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8124' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8123 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8133' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8132 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8138' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8137 [0] = \sq_pos_x [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8153' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8151 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8154' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8151 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8155' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8151 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$8157' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$8156 [0] = \sq_pos_y [2]'. 2.14.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8158' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8191'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8156 [1] = $auto$simplemap.cc:309:simplemap_lut$8189 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8158' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8192' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8191'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8189 [2] = $auto$simplemap.cc:309:simplemap_lut$8189 [1] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8192' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8139' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8173'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8137 [1] = $auto$simplemap.cc:309:simplemap_lut$8170 [2] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8139' from module `\top'. Cell `$auto$simplemap.cc:311:simplemap_lut$8172' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8173'. Redirecting output \Y: $auto$simplemap.cc:309:simplemap_lut$8170 [1] = $auto$simplemap.cc:309:simplemap_lut$8170 [2] Removing $_NOT_ cell `$auto$simplemap.cc:311:simplemap_lut$8172' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6891' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8191'. Redirecting output \Y: $auto$alumacc.cc:474:replace_alu$1153.BB [2] = $auto$simplemap.cc:309:simplemap_lut$8189 [1] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6891' from module `\top'. Cell `$auto$simplemap.cc:37:simplemap_not$6911' is identical to cell `$auto$simplemap.cc:311:simplemap_lut$8173'. Redirecting output \Y: $auto$alumacc.cc:474:replace_alu$1246.BB [2] = $auto$simplemap.cc:309:simplemap_lut$8170 [2] Removing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$6911' from module `\top'. Removed a total of 6 cells. 2.14.16. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removed 16 unused temporary wires. Removed 340 unused cells and 678 unused wires. 2.14.18. Rerunning OPT passes. (Removed registers in this run.) 2.14.19. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1126.slice[2].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[2].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1206.slice[2].carry: CO=\c_ver [2] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1211.slice[2].carry: CO=1'1 2.14.20. Executing OPT_EXPR pass (perform const folding). 2.14.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.22. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 340 unused cells and 678 unused wires. 2.14.24. Rerunning OPT passes. (Removed registers in this run.) 2.14.25. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1126.slice[3].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[3].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1211.slice[3].carry: CO=1'1 2.14.26. Executing OPT_EXPR pass (perform const folding). 2.14.27. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.28. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.29. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 340 unused cells and 678 unused wires. 2.14.30. Rerunning OPT passes. (Removed registers in this run.) 2.14.31. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1126.slice[4].carry: CO=\c_hor [4] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[4].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1211.slice[4].carry: CO=1'1 2.14.32. Executing OPT_EXPR pass (perform const folding). 2.14.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.34. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 340 unused cells and 678 unused wires. 2.14.36. Rerunning OPT passes. (Removed registers in this run.) 2.14.37. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[5].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1211.slice[5].carry: CO=$auto$alumacc.cc:474:replace_alu$1211.BB [5] 2.14.38. Executing OPT_EXPR pass (perform const folding). 2.14.39. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.40. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.41. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 340 unused cells and 678 unused wires. 2.14.42. Rerunning OPT passes. (Removed registers in this run.) 2.14.43. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[6].carry: CO=1'1 2.14.44. Executing OPT_EXPR pass (perform const folding). 2.14.45. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.46. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.47. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 340 unused cells and 678 unused wires. 2.14.48. Rerunning OPT passes. (Removed registers in this run.) 2.14.49. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$1185.slice[7].carry: CO=\c_hor [7] 2.14.50. Executing OPT_EXPR pass (perform const folding). 2.14.51. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.52. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.53. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 340 unused cells and 678 unused wires. 2.14.54. Rerunning OPT passes. (Removed registers in this run.) 2.14.55. Running ICE40 specific optimizations. 2.14.56. Executing OPT_EXPR pass (perform const folding). 2.14.57. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.58. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.59. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 340 unused cells and 678 unused wires. 2.14.60. Finished OPT passes. (There is nothing left to do.) 2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). 2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). Selected cell types for direct conversion: $_DFF_PP1_ -> $__DFFE_PP1 $_DFF_PP0_ -> $__DFFE_PP0 $_DFF_PN1_ -> $__DFFE_PN1 $_DFF_PN0_ -> $__DFFE_PN0 $_DFF_NP1_ -> $__DFFE_NP1 $_DFF_NP0_ -> $__DFFE_NP0 $_DFF_NN1_ -> $__DFFE_NN1 $_DFF_NN0_ -> $__DFFE_NN0 $_DFF_N_ -> $_DFFE_NP_ $_DFF_P_ -> $_DFFE_PP_ Transforming FF to FF+Enable cells in module top: converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$5917 to $_DFFE_PP_ for $memory\sq_figure$wrmux[8][16][0]$y$3488 [0] -> \sq_figure[8] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$5918 to $_DFFE_PP_ for $memory\sq_figure$wrmux[8][16][0]$y$3488 [1] -> \sq_figure[8] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap