=> Building devel/lattice-ice40-examples-hx1k Started : Sunday, 7 JUL 2019 at 17:43:31 UTC Platform: 5.7-DEVELOPMENT DragonFly v5.7.0.83.g49866-DEVELOPMENT #40: Sun Jun 30 03:00:04 PDT 2019 root@pkgbox64.dragonflybsd.org:/usr/obj/usr/src/sys/X86_64_GENERIC x86_64 -------------------------------------------------- -- Environment -------------------------------------------------- UNAME_r=5.4-SYNTH UNAME_m=x86_64 UNAME_p=x86_64 UNAME_v=DragonFly 5.4-SYNTH UNAME_s=DragonFly PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin SSL_NO_VERIFY_PEER=1 TERM=dumb PKG_CACHEDIR=/var/cache/pkg8 PKG_DBDIR=/var/db/pkg8 PORTSDIR=/xports LANG=C HOME=/root USER=root -------------------------------------------------- -- Options -------------------------------------------------- -------------------------------------------------- -- CONFIGURE_ENV -------------------------------------------------- MAKE=gmake XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx1k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx1k HOME=/construction/devel/lattice-ice40-examples-hx1k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx1k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin SHELL=/bin/sh CONFIG_SHELL=/bin/sh CCVER=gcc80 -------------------------------------------------- -- CONFIGURE_ARGS -------------------------------------------------- -------------------------------------------------- -- MAKE_ENV -------------------------------------------------- XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx1k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx1k HOME=/construction/devel/lattice-ice40-examples-hx1k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx1k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" -------------------------------------------------- -- MAKE_ARGS -------------------------------------------------- DESTDIR=/construction/devel/lattice-ice40-examples-hx1k/stage -------------------------------------------------- -- PLIST_SUB -------------------------------------------------- OSREL=5.4 PREFIX=%D LOCALBASE=/usr/local RESETPREFIX=/usr/local LIB32DIR=lib PROFILE="@comment " DOCSDIR="share/doc/lattice-ice40-examples-hx1k" EXAMPLESDIR="share/examples/lattice-ice40-olimex" DATADIR="share/lattice-ice40-examples-hx1k" WWWDIR="www/lattice-ice40-examples-hx1k" ETCDIR="etc/lattice-ice40-examples-hx1k" -------------------------------------------------- -- SUB_LIST -------------------------------------------------- PREFIX=/usr/local LOCALBASE=/usr/local DATADIR=/usr/local/share/lattice-ice40-examples-hx1k DOCSDIR=/usr/local/share/doc/lattice-ice40-examples-hx1k EXAMPLESDIR=/usr/local/share/examples/lattice-ice40-olimex WWWDIR=/usr/local/www/lattice-ice40-examples-hx1k ETCDIR=/usr/local/etc/lattice-ice40-examples-hx1k -------------------------------------------------- -- /etc/make.conf -------------------------------------------------- SYNTHPROFILE=Release-5.4 USE_PACKAGE_DEPENDS_ONLY=yes PACKAGE_BUILDING=yes BATCH=yes PKG_CREATE_VERBOSE=yes PORTSDIR=/xports DISTDIR=/distfiles WRKDIRPREFIX=/construction PORT_DBDIR=/options PACKAGES=/packages MAKE_JOBS_NUMBER_LIMIT=5 HAVE_COMPAT_IA32_KERN= CONFIGURE_MAX_CMD_LEN=262144 _PERL5_FROM_BIN=5.28.1 _ALTCCVERSION_921dbbb2=none _OBJC_ALTCCVERSION_921dbbb2=none _SMP_CPUS=8 UID=0 ARCH=x86_64 OPSYS=DragonFly DFLYVERSION=500400 OSVERSION=9999999 OSREL=5.4 _OSRELEASE=5.4-SYNTH PYTHONBASE=/usr/local _PKG_CHECKED=1 -------------------------------------------------------------------------------- -- Phase: check-sanity -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user -------------------------------------------------------------------------------- -- Phase: pkg-depends -------------------------------------------------------------------------------- ===> lattice-ice40-examples-hx1k-g20180310 depends on file: /usr/local/sbin/pkg - not found ===> Installing existing package /packages/All/pkg-1.11.1.txz Installing pkg-1.11.1... Extracting pkg-1.11.1: .......... done ===> lattice-ice40-examples-hx1k-g20180310 depends on file: /usr/local/sbin/pkg - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310 -------------------------------------------------------------------------------- -- Phase: fetch-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: fetch -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310 for building -------------------------------------------------------------------------------- -- Phase: checksum -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310 for building => SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz. -------------------------------------------------------------------------------- -- Phase: extract-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: extract -------------------------------------------------------------------------------- ===> License APACHE20 accepted by the user ===> Fetching all distfiles required by lattice-ice40-examples-hx1k-g20180310 for building ===> Extracting for lattice-ice40-examples-hx1k-g20180310 => SHA256 Checksum OK for OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz. -------------------------------------------------------------------------------- -- Phase: patch-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: patch -------------------------------------------------------------------------------- ===> Patching for lattice-ice40-examples-hx1k-g20180310 -------------------------------------------------------------------------------- -- Phase: build-depends -------------------------------------------------------------------------------- ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: abc - not found ===> Installing existing package /packages/All/abc-g20180420_1.txz Installing abc-g20180420_1... `-- Installing readline-8.0.0... | `-- Installing indexinfo-0.3.1... | `-- Extracting indexinfo-0.3.1: .... done | `-- Installing ncurses-6.1.20190525... | `-- Extracting ncurses-6.1.20190525: .......... done `-- Extracting readline-8.0.0: .......... done Extracting abc-g20180420_1: ....... done ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: abc - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310 ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: arachne-pnr - not found ===> Installing existing package /packages/All/arachne-pnr-g20181021_1.txz Installing arachne-pnr-g20181021_1... Extracting arachne-pnr-g20181021_1: ......... done ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: arachne-pnr - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310 ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: icepack - not found ===> Installing existing package /packages/All/icestorm-g20181021_1.txz Installing icestorm-g20181021_1... `-- Installing libftdi1-1.4_11... | `-- Installing boost-libs-1.70.0_2... | | `-- Installing icu-64.2,1... | | `-- Extracting icu-64.2,1: .......... done | `-- Extracting boost-libs-1.70.0_2: .......... done | `-- Installing gettext-runtime-0.20.1... | `-- Extracting gettext-runtime-0.20.1: .......... done | `-- Installing libconfuse-3.2.1_1... | `-- Extracting libconfuse-3.2.1_1: .......... done | `-- Installing python27-2.7.16_1... | | `-- Installing expat-2.2.6_1... | | `-- Extracting expat-2.2.6_1: .......... done | | `-- Installing libffi-3.2.1_3... | | `-- Extracting libffi-3.2.1_3: .......... done | | `-- Installing libressl-2.9.2... | | `-- Extracting libressl-2.9.2: .......... done | `-- Extracting python27-2.7.16_1: .......... done `-- Extracting libftdi1-1.4_11: .......... done `-- Installing python36-3.6.8_2... `-- Extracting python36-3.6.8_2: .......... done Extracting icestorm-g20181021_1: .......... done Message from boost-libs-1.70.0_2: You have built the Boost library with thread support. Don't forget to add -pthread to your linker options when linking your code. Message from python27-2.7.16_1: =========================================================================== Note that some standard Python modules are provided as separate ports as they require additional dependencies. They are available as: bsddb databases/py-bsddb gdbm databases/py-gdbm sqlite3 databases/py-sqlite3 tkinter x11-toolkits/py-tkinter =========================================================================== Message from python36-3.6.8_2: =========================================================================== Note that some standard Python modules are provided as separate ports as they require additional dependencies. They are available as: py36-gdbm databases/py-gdbm@py36 py36-sqlite3 databases/py-sqlite3@py36 py36-tkinter x11-toolkits/py-tkinter@py36 =========================================================================== ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: icepack - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310 ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: yosys - not found ===> Installing existing package /packages/All/yosys-0.8_2.txz Installing yosys-0.8_2... `-- Installing tcl86-8.6.9_1... `-- Extracting tcl86-8.6.9_1: .......... done Extracting yosys-0.8_2: .......... done ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: yosys - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310 ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: gmake - not found ===> Installing existing package /packages/All/gmake-4.2.1_3.txz Installing gmake-4.2.1_3... Extracting gmake-4.2.1_3: .......... done ===> lattice-ice40-examples-hx1k-g20180310 depends on executable: gmake - found ===> Returning to build of lattice-ice40-examples-hx1k-g20180310 -------------------------------------------------------------------------------- -- Phase: lib-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: configure -------------------------------------------------------------------------------- ===> Configuring for lattice-ice40-examples-hx1k-g20180310 -------------------------------------------------------------------------------- -- Phase: build -------------------------------------------------------------------------------- ===> Building for lattice-ice40-examples-hx1k-g20180310 /usr/bin/env XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx1k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx1k HOME=/construction/devel/lattice-ice40-examples-hx1k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx1k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -j5 -C /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb gmake[1]: Entering directory '/construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb' yosys -p 'synth_ice40 -top top -blif example.blif' example.v /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 UNKNOWN, c++ 8.1 -O2 -fno-strict-aliasing -fPIC -Os) -- Parsing `example.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `example.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. -- Running command `synth_ice40 -top top -blif example.blif' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Analyzing design hierarchy.. Top module: \top 2.2.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\top.$proc$example.v:23$20'. Set init value: \mode = 1'1 Found init rule in `\top.$proc$example.v:22$19'. Set init value: \rst_cnt = 15'000000000000000 2.3.4. Executing PROC_ARST pass (detect async resets in processes). 2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$proc$example.v:23$20'. 1/1: $1\mode[0:0] Creating decoders for process `\top.$proc$example.v:22$19'. 1/1: $1\rst_cnt[14:0] Creating decoders for process `\top.$proc$example.v:38$5'. 1/9: $0\LED2_m0_r[0:0] 2/9: $0\LED1_m0_r[0:0] 3/9: $0\cntr[14:0] 4/9: $0\BUT2_r[0:0] 5/9: $0\BUT1_r[0:0] 6/9: $0\mode[0:0] 7/9: $0\rst_cnt[14:0] 8/9: $0\LED2_m1_r[0:0] 9/9: $0\LED1_m1_r[0:0] Creating decoders for process `\top.$proc$example.v:34$3'. 1/1: $0\clk_div[11:0] 2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\BUT1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$45' with positive edge clock. Creating register for signal `\top.\BUT2_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$46' with positive edge clock. Creating register for signal `\top.\LED1_m0_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$47' with positive edge clock. Creating register for signal `\top.\LED2_m0_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$48' with positive edge clock. Creating register for signal `\top.\LED1_m1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$49' with positive edge clock. Creating register for signal `\top.\LED2_m1_r' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$50' with positive edge clock. Creating register for signal `\top.\cntr' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$51' with positive edge clock. Creating register for signal `\top.\rst_cnt' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$52' with positive edge clock. Creating register for signal `\top.\mode' using process `\top.$proc$example.v:38$5'. created $dff cell `$procdff$53' with positive edge clock. Creating register for signal `\top.\clk_div' using process `\top.$proc$example.v:34$3'. created $dff cell `$procdff$54' with positive edge clock. 2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `top.$proc$example.v:23$20'. Removing empty process `top.$proc$example.v:22$19'. Found and cleaned up 4 empty switches in `\top.$proc$example.v:38$5'. Removing empty process `top.$proc$example.v:38$5'. Removing empty process `top.$proc$example.v:34$3'. Cleaned up 4 empty switches. 2.4. Executing FLATTEN pass (flatten design). No more expansions possible. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing SYNTH pass. 2.7.1. Executing PROC pass (convert processes to netlists). 2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.7.1.3. Executing PROC_INIT pass (extract init attributes). 2.7.1.4. Executing PROC_ARST pass (detect async resets in processes). 2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs). 2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.7.2. Executing OPT_EXPR pass (perform const folding). Replacing $eq cell `$eq$example.v:43$7' in module `top' with inverter. Replacing $eq cell `$eq$example.v:47$9' in module `top' with inverter. Replacing $eq cell `$eq$example.v:47$10' in module `top' with inverter. Replacing $eq cell `$eq$example.v:47$12' (1) in module `\top' with constant driver `$eq$example.v:47$12_Y = \reset'. Optimizing away select inverter for $mux cell `$procmux$28' in module `top'. 2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$not' cell `$eq$example.v:43$7'. removed 24 unused temporary wires. Removed 1 unused cells and 24 unused wires. 2.7.4. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.7.5. Executing OPT pass (performing simple optimizations). 2.7.5.1. Executing OPT_EXPR pass (perform const folding). 2.7.5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$not$example.v:52$15' is identical to cell `$eq$example.v:47$9'. Redirecting output \Y: $0\LED1_m0_r[0:0] = $eq$example.v:47$9_Y Removing $not cell `$not$example.v:52$15' from module `\top'. Cell `$not$example.v:53$16' is identical to cell `$eq$example.v:47$10'. Redirecting output \Y: $0\LED2_m0_r[0:0] = $eq$example.v:47$10_Y Removing $not cell `$not$example.v:53$16' from module `\top'. Removed a total of 2 cells. 2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Replacing known input bits on port B of cell $procmux$28: \rst_cnt -> { 1'1 \rst_cnt [13:0] } Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.7.5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removed 2 unused temporary wires. Removed 1 unused cells and 26 unused wires. 2.7.5.8. Executing OPT_EXPR pass (perform const folding). 2.7.5.9. Finished OPT passes. (There is nothing left to do.) 2.7.6. Executing WREDUCE pass (reducing word size of cells). Removed top 11 bits (of 12) from port B of cell top.$add$example.v:35$4 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:41$6 ($add). Removed top 14 bits (of 15) from port B of cell top.$add$example.v:44$8 ($add). Removed top 1 bits (of 15) from port B of cell top.$eq$example.v:55$17 ($eq). 2.7.7. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $add$example.v:35$4 ($add). creating $macc model for $add$example.v:41$6 ($add). creating $macc model for $add$example.v:44$8 ($add). creating $alu model for $macc $add$example.v:44$8. creating $alu model for $macc $add$example.v:41$6. creating $alu model for $macc $add$example.v:35$4. creating $alu model for $gt$example.v:59$18 ($gt): new $alu creating $alu cell for $gt$example.v:59$18: $auto$alumacc.cc:474:replace_alu$56 creating $alu cell for $add$example.v:35$4: $auto$alumacc.cc:474:replace_alu$67 creating $alu cell for $add$example.v:41$6: $auto$alumacc.cc:474:replace_alu$70 creating $alu cell for $add$example.v:44$8: $auto$alumacc.cc:474:replace_alu$73 created 4 $alu and 0 $macc cells. 2.7.8. Executing SHARE pass (SAT-based resource sharing). 2.7.9. Executing OPT pass (performing simple optimizations). 2.7.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing away select inverter for $mux cell `$procmux$22' in module `top'. Optimizing away select inverter for $mux cell `$procmux$37' in module `top'. Optimizing away select inverter for $mux cell `$procmux$43' in module `top'. 2.7.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$59: { $auto$alumacc.cc:490:replace_alu$57 [0] $auto$alumacc.cc:490:replace_alu$57 [1] $auto$alumacc.cc:490:replace_alu$57 [2] $auto$alumacc.cc:490:replace_alu$57 [3] $auto$alumacc.cc:490:replace_alu$57 [4] $auto$alumacc.cc:490:replace_alu$57 [5] $auto$alumacc.cc:490:replace_alu$57 [6] $auto$alumacc.cc:490:replace_alu$57 [7] $auto$alumacc.cc:490:replace_alu$57 [8] $auto$alumacc.cc:490:replace_alu$57 [9] $auto$alumacc.cc:490:replace_alu$57 [10] $auto$alumacc.cc:490:replace_alu$57 [11] $auto$alumacc.cc:490:replace_alu$57 [12] $auto$alumacc.cc:490:replace_alu$57 [13] $auto$alumacc.cc:490:replace_alu$57 [14] } Optimizing cells in module \top. Performed a total of 1 changes. 2.7.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$not' cell `$auto$alumacc.cc:58:get_gt$65'. removed 2 unused temporary wires. Removed 2 unused cells and 28 unused wires. 2.7.9.8. Executing OPT_EXPR pass (perform const folding). 2.7.9.9. Rerunning OPT passes. (Maybe there is more to do..) 2.7.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.7.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.7.9.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.9.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.9.15. Executing OPT_EXPR pass (perform const folding). 2.7.9.16. Finished OPT passes. (There is nothing left to do.) 2.7.10. Executing FSM pass (extract and optimize FSM). 2.7.10.1. Executing FSM_DETECT pass (finding FSMs in design). 2.7.10.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.7.10.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.7.10.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.10.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.7.10.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.7.10.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.7.10.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.7.11. Executing OPT pass (performing simple optimizations). 2.7.11.1. Executing OPT_EXPR pass (perform const folding). 2.7.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.7.11.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.11.5. Finished fast OPT passes. 2.7.12. Executing MEMORY pass. 2.7.12.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 2.7.12.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.12.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.7.12.5. Executing MEMORY_COLLECT pass (generating $mem cells). 2.7.13. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). 2.9. Executing TECHMAP pass (map to technology primitives). 2.9.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. No more expansions possible. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.10.5. Finished fast OPT passes. 2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$22 (pure) Root of a mux tree: $procmux$25 (pure) Root of a mux tree: $procmux$31 (pure) Root of a mux tree: $procmux$37 (pure) Root of a mux tree: $procmux$43 (pure) Root of a mux tree: $ternary$example.v:30$1 (pure) Root of a mux tree: $ternary$example.v:31$2 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.12.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 28 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). 2.12.9. Finished OPT passes. (There is nothing left to do.) 2.13. Executing TECHMAP pass (map to technology primitives). 2.13.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.13.2. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. Mapping top.$ternary$example.v:30$1 ($mux) with simplemap. Mapping top.$ternary$example.v:31$2 ($mux) with simplemap. 2.13.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 15 Parameter \B_WIDTH = 15 Parameter \Y_WIDTH = 15 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=15\B_WIDTH=15\Y_WIDTH=15'. 2.13.4. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$56 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=15\B_WIDTH=15\Y_WIDTH=15. Mapping top.$eq$example.v:47$9 ($not) with simplemap. Mapping top.$eq$example.v:47$10 ($not) with simplemap. Mapping top.$logic_and$example.v:47$11 ($logic_and) with simplemap. Mapping top.$logic_and$example.v:47$13 ($logic_and) with simplemap. Mapping top.$xor$example.v:48$14 ($xor) with simplemap. Mapping top.$auto$alumacc.cc:64:get_eq$59 ($reduce_and) with simplemap. Mapping top.$eq$example.v:55$17 ($eq) with simplemap. 2.13.5. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 15 Parameter \Y_WIDTH = 15 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=15\Y_WIDTH=15'. 2.13.6. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$73 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=15\Y_WIDTH=15. Mapping top.$procmux$22 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$70 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=15\Y_WIDTH=15. Mapping top.$procmux$25 ($mux) with simplemap. Mapping top.$procmux$28 ($mux) with simplemap. 2.13.7. Executing AST frontend in derive mode using pre-parsed AST for module `\_80_ice40_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \B_WIDTH = 12 Parameter \Y_WIDTH = 12 Generating RTLIL representation for module `$paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=12\Y_WIDTH=12'. 2.13.8. Continuing TECHMAP pass. Mapping top.$auto$alumacc.cc:474:replace_alu$67 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=12\Y_WIDTH=12. Mapping top.$procmux$31 ($mux) with simplemap. Mapping top.$procmux$34 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:58:get_gt$63 ($or) with simplemap. Mapping top.$procmux$37 ($mux) with simplemap. Mapping top.$procmux$40 ($mux) with simplemap. Mapping top.$auto$alumacc.cc:78:get_cf$61 ($not) with simplemap. Mapping top.$procmux$43 ($mux) with simplemap. Mapping top.$procdff$45 ($dff) with simplemap. Mapping top.$procdff$46 ($dff) with simplemap. Mapping top.$procdff$47 ($dff) with simplemap. Mapping top.$procdff$48 ($dff) with simplemap. Mapping top.$procdff$49 ($dff) with simplemap. Mapping top.$procdff$50 ($dff) with simplemap. Mapping top.$procdff$51 ($dff) with simplemap. Mapping top.$procdff$52 ($dff) with simplemap. Mapping top.$procdff$53 ($dff) with simplemap. Mapping top.$procdff$54 ($dff) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$56.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$56.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$73.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$193 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$73.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$73.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$70.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$193 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$70.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$70.A_conv ($pos) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229 ($xor) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228 ($mux) with simplemap. Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$67.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$227 ($not) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$67.B_conv ($pos) with simplemap. Mapping top.$auto$alumacc.cc:474:replace_alu$67.A_conv ($pos) with simplemap. No more expansions possible. 2.14. Executing ICE40_OPT pass (performing simple optimizations). 2.14.1. Running ICE40 specific optimizations. 2.14.2. Executing OPT_EXPR pass (perform const folding). Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$330' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [0] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$315' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [0] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$343' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [13] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$328' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [13] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$344' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [14] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$329' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [14] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$314' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [14] = \cntr [14]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$341' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [11] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$326' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [11] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$311' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [11] = \cntr [11]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$342' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [12] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$327' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [12] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$312' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [12] = \cntr [12]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$339' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [9] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$324' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [9] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$309' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [9] = \cntr [9]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$340' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [10] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$325' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [10] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$310' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [10] = \cntr [10]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$337' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$322' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [7] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$338' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [8] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$323' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [8] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$308' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [8] = \cntr [8]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$335' (0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [5] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$320' (011) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [5] = 1'1'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$336' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$321' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [6] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$306' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [6] = \cntr [6]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$333' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$318' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [3] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$303' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [3] = \cntr [3]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$334' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [4] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$319' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [4] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$304' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [4] = \cntr [4]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$331' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [1] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$316' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [1] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$301' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [1] = \cntr [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$332' (1) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$128_Y [2] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$317' (101) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$129_Y [2] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$302' (?0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [2] = \cntr [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$160' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [4] = \cntr [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$162' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [6] = \cntr [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$168' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [12] = \cntr [12]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$170' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$154 [14] = \cntr [14]'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$245' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$248' in module `top'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$360' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [0] = \rst_cnt [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$361' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [1] = \rst_cnt [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$346' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [1] = \rst_cnt [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$362' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [2] = \rst_cnt [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$347' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [2] = \rst_cnt [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$363' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [3] = \rst_cnt [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$348' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [3] = \rst_cnt [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$364' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [4] = \rst_cnt [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$349' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [4] = \rst_cnt [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$365' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [5] = \rst_cnt [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$350' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [5] = \rst_cnt [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$366' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [6] = \rst_cnt [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$351' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [6] = \rst_cnt [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$367' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [7] = \rst_cnt [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$352' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [7] = \rst_cnt [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$368' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [8] = \rst_cnt [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$353' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [8] = \rst_cnt [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$369' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [9] = \rst_cnt [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$354' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [9] = \rst_cnt [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$370' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [10] = \rst_cnt [10]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$355' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [10] = \rst_cnt [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$371' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [11] = \rst_cnt [11]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$356' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [11] = \rst_cnt [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$372' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [12] = \rst_cnt [12]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$357' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [12] = \rst_cnt [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$373' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [13] = \rst_cnt [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$358' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [13] = \rst_cnt [13]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$374' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [14] = \rst_cnt [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$359' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$73.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [14] = \rst_cnt [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$405' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [0] = \cntr [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$406' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [1] = \cntr [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$391' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [1] = \cntr [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$407' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [2] = \cntr [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$392' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [2] = \cntr [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$408' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [3] = \cntr [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$393' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [3] = \cntr [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$409' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [4] = \cntr [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$394' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [4] = \cntr [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$410' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [5] = \cntr [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$395' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [5] = \cntr [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$411' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [6] = \cntr [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$396' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [6] = \cntr [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$412' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [7] = \cntr [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$397' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [7] = \cntr [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$413' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [8] = \cntr [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$398' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [8] = \cntr [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$414' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [9] = \cntr [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$399' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [9] = \cntr [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$415' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [10] = \cntr [10]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$400' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [10] = \cntr [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$416' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [11] = \cntr [11]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$401' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [11] = \cntr [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$417' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [12] = \cntr [12]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$402' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [12] = \cntr [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$418' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [13] = \cntr [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$403' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [13] = \cntr [13]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$419' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$194_Y [14] = \cntr [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$404' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [14] = \cntr [14]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$447' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [0] = \clk_div [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$448' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [1] = \clk_div [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$436' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [1] = \clk_div [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$449' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [2] = \clk_div [2]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$437' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [2] = \clk_div [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$450' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [3] = \clk_div [3]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$438' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [3] = \clk_div [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$451' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [4] = \clk_div [4]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$439' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [4] = \clk_div [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$452' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [5] = \clk_div [5]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$440' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [5] = \clk_div [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$453' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [6] = \clk_div [6]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$441' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [6] = \clk_div [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$454' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [7] = \clk_div [7]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$442' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [7] = \clk_div [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$455' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [8] = \clk_div [8]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$443' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [8] = \clk_div [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$456' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [9] = \clk_div [9]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$444' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [9] = \clk_div [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$457' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [10] = \clk_div [10]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$445' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [10] = \clk_div [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$458' (??0) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$228_Y [11] = \clk_div [11]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$446' (0?) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$67.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$229_Y [11] = \clk_div [11]'. 2.14.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$300' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$390'. Redirecting output \Y: $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [0] = $techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$300' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$169' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$313'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [13] = $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [13] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$169' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$163' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$307'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [7] = $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [7] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$163' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$161' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$305'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [5] = $techmap$auto$alumacc.cc:474:replace_alu$56.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$130_Y [5] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$161' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$156' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$390'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$154 [0] = $techmap$auto$alumacc.cc:474:replace_alu$70.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$195_Y [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$156' from module `\top'. Removed a total of 5 cells. 2.14.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[14].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[13].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[12].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[11].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[10].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[9].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[8].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[7].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[6].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[5].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[4].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[3].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[2].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[1].adder'. removing unused `\SB_LUT4' cell `$auto$alumacc.cc:474:replace_alu$56.slice[0].adder'. removing unused `$_NOT_' cell `$auto$simplemap.cc:206:simplemap_lognot$192'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$73.slice[14].carry'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$70.slice[14].carry'. removing unused `\SB_CARRY' cell `$auto$alumacc.cc:474:replace_alu$67.slice[11].carry'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$345'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$375'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$376'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$377'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$378'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$379'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$380'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$381'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$382'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$383'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$384'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$385'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$386'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$387'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$388'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$389'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$420'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$421'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$422'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$423'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$424'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$425'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$426'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$427'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$428'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$429'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$430'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$431'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$432'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$433'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$434'. removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$435'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$459'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$460'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$461'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$462'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$463'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$464'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$465'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$466'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$467'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$468'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$469'. removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$470'. removed 70 unused temporary wires. Removed 65 unused cells and 98 unused wires. 2.14.6. Rerunning OPT passes. (Removed registers in this run.) 2.14.7. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$56.slice[0].carry: CO=1'1 Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$67.slice[0].carry: CO=\clk_div [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$70.slice[0].carry: CO=\cntr [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$73.slice[0].carry: CO=\rst_cnt [0] Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$67.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$70.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$73.slice[1].adder back to logic. 2.14.8. Executing OPT_EXPR pass (perform const folding). Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$517' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$516' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$522' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$514' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$515' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$521' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$513' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$512' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$520' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$511' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$510' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$509 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$519' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$518 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$524' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$523 [0] = \rst_cnt [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$498' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$497' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$503' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$496' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$495' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$502' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$494' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$493' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$501' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$492' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$491' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$490 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$500' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$499 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$505' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$504 [0] = \cntr [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$479' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [7] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$478' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [6] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$484' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$477' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [5] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$476' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [4] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$483' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$475' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [3] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$474' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [2] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$482' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$473' (100) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$472' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$471 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$481' (010) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$480 [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$486' (01?) in module `\top' with constant driver `$auto$simplemap.cc:309:simplemap_lut$485 [0] = \clk_div [1]'. 2.14.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removed 9 unused temporary wires. Removed 65 unused cells and 107 unused wires. 2.14.12. Rerunning OPT passes. (Removed registers in this run.) 2.14.13. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$56.slice[1].carry: CO=\cntr [1] 2.14.14. Executing OPT_EXPR pass (perform const folding). 2.14.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.16. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 65 unused cells and 107 unused wires. 2.14.18. Rerunning OPT passes. (Removed registers in this run.) 2.14.19. Running ICE40 specific optimizations. 2.14.20. Executing OPT_EXPR pass (perform const folding). 2.14.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.14.22. Executing OPT_RMDFF pass (remove dff with constant values). 2.14.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 65 unused cells and 107 unused wires. 2.14.24. Finished OPT passes. (There is nothing left to do.) 2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). 2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). Selected cell types for direct conversion: $_DFF_PP1_ -> $__DFFE_PP1 $_DFF_PP0_ -> $__DFFE_PP0 $_DFF_PN1_ -> $__DFFE_PN1 $_DFF_PN0_ -> $__DFFE_PN0 $_DFF_NP1_ -> $__DFFE_NP1 $_DFF_NP0_ -> $__DFFE_NP0 $_DFF_NN1_ -> $__DFFE_NN1 $_DFF_NN0_ -> $__DFFE_NN0 $_DFF_N_ -> $_DFFE_NP_ $_DFF_P_ -> $_DFFE_PP_ Transforming FF to FF+Enable cells in module top: converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$255 to $_DFFE_PP_ for $0\LED1_m1_r[0:0] -> \LED1_m1_r. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$256 to $_DFFE_PP_ for $0\LED2_m1_r[0:0] -> \LED2_m1_r. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$258 to $_DFFE_PP_ for $0\cntr[14:0] [1] -> \cntr [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$272 to $_DFFE_PP_ for $0\rst_cnt[14:0] [0] -> \rst_cnt [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$273 to $_DFFE_PP_ for $0\rst_cnt[14:0] [1] -> \rst_cnt [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$274 to $_DFFE_PP_ for $0\rst_cnt[14:0] [2] -> \rst_cnt [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$275 to $_DFFE_PP_ for $0\rst_cnt[14:0] [3] -> \rst_cnt [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$276 to $_DFFE_PP_ for $0\rst_cnt[14:0] [4] -> \rst_cnt [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$277 to $_DFFE_PP_ for $0\rst_cnt[14:0] [5] -> \rst_cnt [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$278 to $_DFFE_PP_ for $0\rst_cnt[14:0] [6] -> \rst_cnt [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$279 to $_DFFE_PP_ for $0\rst_cnt[14:0] [7] -> \rst_cnt [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$280 to $_DFFE_PP_ for $0\rst_cnt[14:0] [8] -> \rst_cnt [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$281 to $_DFFE_PP_ for $0\rst_cnt[14:0] [9] -> \rst_cnt [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$282 to $_DFFE_PP_ for $0\rst_cnt[14:0] [10] -> \rst_cnt [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$283 to $_DFFE_PP_ for $0\rst_cnt[14:0] [11] -> \rst_cnt [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$284 to $_DFFE_PP_ for $0\rst_cnt[14:0] [12] -> \rst_cnt [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$285 to $_DFFE_PP_ for $0\rst_cnt[14:0] [13] -> \rst_cnt [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$287 to $_DFFE_PP_ for $0\mode[0:0] -> \mode. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$289 to $_DFFE_PP_ for $0\clk_div[11:0] [1] -> \clk_div [1]. 2.17. Executing TECHMAP pass (map to technology primitives). 2.17.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Successfully finished Verilog frontend. Mapping top.$auto$simplemap.cc:420:simplemap_dff$299 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$251 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$252 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$253 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$254 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$255 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$256 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$257 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$258 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$259 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$260 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$261 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$262 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$263 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$264 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$265 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$266 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$267 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$268 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$269 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$270 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$271 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$272 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$273 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$274 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$275 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$276 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$277 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$278 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$279 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$280 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$281 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$282 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$283 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$284 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$285 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$286 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$287 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$288 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$289 using \$_DFFE_PP_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$290 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$291 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$292 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$293 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$294 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$295 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$296 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$297 using \$_DFF_P_. Mapping top.$auto$simplemap.cc:420:simplemap_dff$298 using \$_DFF_P_. No more expansions possible. 2.18. Executing OPT_EXPR pass (perform const folding). Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$612' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$609 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$603' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$600 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$594' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$591 [1] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$527' (x??) in module `\top' with constant driver `$add$example.v:44$8_Y [1] = $auto$simplemap.cc:309:simplemap_lut$523 [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$569' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$566 [1] = \rst_cnt [14]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$568' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$566 [0] = \rst_cnt [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$707' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$705 = \clk_div [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$701' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$699 = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$693' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$690 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$684' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$681 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$581' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$578 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$570' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$566 [2] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$508' (x??) in module `\top' with constant driver `$add$example.v:41$6_Y [1] = $auto$simplemap.cc:309:simplemap_lut$504 [1]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$550' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$548 [0] = \cntr [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$560' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$557 [1] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$211' (x??) in module `\top' with constant driver `$0\mode[0:0] = $xor$example.v:48$14_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$212' (?x?) in module `\top' with constant driver `$procmux$28_Y [0] = $add$example.v:44$8_Y [0]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$213' (?x?) in module `\top' with constant driver `$procmux$28_Y [1] = $auto$simplemap.cc:309:simplemap_lut$523 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$214' (?x?) in module `\top' with constant driver `$procmux$28_Y [2] = $add$example.v:44$8_Y [2]'. Replacing $_MUX_ cell `$auto$simplemap.cc:311:simplemap_lut$489' (x??) in module `\top' with constant driver `$0\clk_div[11:0] [1] = $auto$simplemap.cc:309:simplemap_lut$485 [1]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$215' (?x?) in module `\top' with constant driver `$procmux$28_Y [3] = $add$example.v:44$8_Y [3]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$216' (?x?) in module `\top' with constant driver `$procmux$28_Y [4] = $add$example.v:44$8_Y [4]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$217' (?x?) in module `\top' with constant driver `$procmux$28_Y [5] = $add$example.v:44$8_Y [5]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$218' (?x?) in module `\top' with constant driver `$procmux$28_Y [6] = $add$example.v:44$8_Y [6]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$219' (?x?) in module `\top' with constant driver `$procmux$28_Y [7] = $add$example.v:44$8_Y [7]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$220' (?x?) in module `\top' with constant driver `$procmux$28_Y [8] = $add$example.v:44$8_Y [8]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$221' (?x?) in module `\top' with constant driver `$procmux$28_Y [9] = $add$example.v:44$8_Y [9]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$222' (?x?) in module `\top' with constant driver `$procmux$28_Y [10] = $add$example.v:44$8_Y [10]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$223' (?x?) in module `\top' with constant driver `$procmux$28_Y [11] = $add$example.v:44$8_Y [11]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$224' (?x?) in module `\top' with constant driver `$procmux$28_Y [12] = $add$example.v:44$8_Y [12]'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$225' (?x?) in module `\top' with constant driver `$procmux$28_Y [13] = $add$example.v:44$8_Y [13]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$675' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$672 [1] = $logic_and$example.v:47$13_Y'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$245' (1x?) in module `\top' with constant driver `$procmux$34_Y = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$247' (01?) in module `\top' with constant driver `$0\LED2_m1_r[0:0] = $auto$rtlil.cc:1698:Or$64'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$248' (0x?) in module `\top' with constant driver `$procmux$40_Y = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$666' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$663 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$657' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$654 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$648' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$645 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$639' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$636 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$630' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$627 [1] = $logic_and$example.v:47$13_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$621' (?0) in module `\top' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$618 [1] = $logic_and$example.v:47$13_Y'. 2.19. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.20. Executing ICE40_FFINIT pass (implement FF init values). Handling FF init values in top. FF init value for cell $auto$simplemap.cc:420:simplemap_dff$272 (SB_DFFE): \rst_cnt [0] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$273 (SB_DFFE): \rst_cnt [1] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$274 (SB_DFFE): \rst_cnt [2] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$275 (SB_DFFE): \rst_cnt [3] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$276 (SB_DFFE): \rst_cnt [4] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$277 (SB_DFFE): \rst_cnt [5] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$278 (SB_DFFE): \rst_cnt [6] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$279 (SB_DFFE): \rst_cnt [7] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$280 (SB_DFFE): \rst_cnt [8] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$281 (SB_DFFE): \rst_cnt [9] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$282 (SB_DFFE): \rst_cnt [10] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$283 (SB_DFFE): \rst_cnt [11] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$284 (SB_DFFE): \rst_cnt [12] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$285 (SB_DFFE): \rst_cnt [13] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$286 (SB_DFF): \rst_cnt [14] = 0 FF init value for cell $auto$simplemap.cc:420:simplemap_dff$287 (SB_DFFE): \mode = 1 2.21. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells). Merging set/reset $_MUX_ cells into SB_FFs in top. Merging $auto$simplemap.cc:277:simplemap_mux$196 (A=1'0, B=$add$example.v:41$6_Y [0], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$257 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$197 (A=1'0, B=$auto$simplemap.cc:309:simplemap_lut$504 [1], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$258 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$198 (A=1'0, B=$add$example.v:41$6_Y [2], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$259 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$199 (A=1'0, B=$add$example.v:41$6_Y [3], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$260 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$200 (A=1'0, B=$add$example.v:41$6_Y [4], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$261 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$201 (A=1'0, B=$add$example.v:41$6_Y [5], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$262 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$202 (A=1'0, B=$add$example.v:41$6_Y [6], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$263 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$203 (A=1'0, B=$add$example.v:41$6_Y [7], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$264 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$204 (A=1'0, B=$add$example.v:41$6_Y [8], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$265 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$205 (A=1'0, B=$add$example.v:41$6_Y [9], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$266 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$206 (A=1'0, B=$add$example.v:41$6_Y [10], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$267 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$207 (A=1'0, B=$add$example.v:41$6_Y [11], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$268 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$208 (A=1'0, B=$add$example.v:41$6_Y [12], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$269 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$209 (A=1'0, B=$add$example.v:41$6_Y [13], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$270 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$210 (A=1'0, B=$add$example.v:41$6_Y [14], S=$auto$rtlil.cc:1698:Or$64) into $auto$simplemap.cc:420:simplemap_dff$271 (SB_DFF). Merging $auto$simplemap.cc:277:simplemap_mux$230 (A=$add$example.v:44$8_Y [0], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$272 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$231 (A=$auto$simplemap.cc:309:simplemap_lut$523 [1], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$273 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$232 (A=$add$example.v:44$8_Y [2], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$274 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$233 (A=$add$example.v:44$8_Y [3], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$275 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$234 (A=$add$example.v:44$8_Y [4], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$276 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$235 (A=$add$example.v:44$8_Y [5], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$277 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$236 (A=$add$example.v:44$8_Y [6], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$278 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$237 (A=$add$example.v:44$8_Y [7], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$279 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$238 (A=$add$example.v:44$8_Y [8], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$280 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$239 (A=$add$example.v:44$8_Y [9], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$281 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$240 (A=$add$example.v:44$8_Y [10], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$282 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$241 (A=$add$example.v:44$8_Y [11], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$283 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$242 (A=$add$example.v:44$8_Y [12], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$284 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$243 (A=$add$example.v:44$8_Y [13], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$285 (SB_DFFE). Merging $auto$simplemap.cc:277:simplemap_mux$244 (A=$procmux$28_Y [14], B=1'0, S=$logic_and$example.v:47$13_Y) into $auto$simplemap.cc:420:simplemap_dff$286 (SB_DFF). 2.22. Executing ICE40_OPT pass (performing simple optimizations). 2.22.1. Running ICE40 specific optimizations. 2.22.2. Executing OPT_EXPR pass (perform const folding). Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$126' in module `top'. Optimizing away select inverter for $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$127' in module `top'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$196' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$197' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$198' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$199' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$200' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$201' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$202' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$203' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$204' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$205' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$206' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$207' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$208' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$209' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$210' in module `top' with and-gate. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$226' in module `top' with or-gate. 2.22.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$798' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$799 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$798' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$796' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$797 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$796' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$794' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$795 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$794' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$792' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$793 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$792' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$790' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$791 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$790' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$788' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$789 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$788' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$786' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$787 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$786' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$784' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$785 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$784' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$782' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$783 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$782' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$780' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$781 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$780' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$778' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$779 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$778' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$776' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$777 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$776' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$774' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$775 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$774' from module `\top'. Cell `$auto$ice40_ffssr.cc:106:execute$772' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $auto$rtlil.cc:1804:NotGate$773 = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$772' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$665' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$663 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$665' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$559' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$557 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$559' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$656' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$654 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$656' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$669' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$661 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$669' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$541' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$551'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$539 [0] = $auto$simplemap.cc:250:simplemap_eqne$548 [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$541' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$532' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$551'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$530 [0] = $auto$simplemap.cc:250:simplemap_eqne$548 [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$532' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$533' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$542'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$530 [1] = $auto$simplemap.cc:250:simplemap_eqne$539 [1] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$533' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$536' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$545'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$528 = $auto$dff2dffe.cc:158:make_patterns_logic$537 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$536' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$692' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$690 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$692' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$660' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$652 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$660' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$647' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$645 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$647' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$638' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$636 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$638' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$642' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$634 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$642' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$629' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$627 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$629' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$580' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$578 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$580' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$633' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$625 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$633' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$620' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$618 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$620' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$624' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$616 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$624' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$611' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$609 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$611' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$602' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$600 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$602' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$687' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$679 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$687' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$606' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$598 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$606' from module `\top'. Cell `$auto$simplemap.cc:277:simplemap_mux$250' is identical to cell `$auto$ice40_ffssr.cc:106:execute$800'. Redirecting output \Y: $0\LED1_m1_r[0:0] = $auto$rtlil.cc:1804:NotGate$801 Removing $_NOT_ cell `$auto$simplemap.cc:277:simplemap_mux$250' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$651' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$643 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$651' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$593' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$591 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$593' from module `\top'. Cell `$auto$simplemap.cc:85:simplemap_bitop$674' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$683'. Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$672 [0] = $auto$simplemap.cc:250:simplemap_eqne$681 [0] Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$674' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$615' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$563'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$607 = $auto$dff2dffe.cc:158:make_patterns_logic$555 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$615' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$563' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$555 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$563' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$584' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$576 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$584' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$678' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$670 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$678' from module `\top'. Cell `$auto$simplemap.cc:136:simplemap_reduce$696' is identical to cell `$auto$simplemap.cc:136:simplemap_reduce$597'. Redirecting output \Y: $auto$dff2dffe.cc:158:make_patterns_logic$688 = $auto$dff2dffe.cc:158:make_patterns_logic$589 Removing $_OR_ cell `$auto$simplemap.cc:136:simplemap_reduce$696' from module `\top'. Removed a total of 45 cells. 2.22.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$196'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$197'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$198'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$199'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$200'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$201'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$202'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$203'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$204'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$205'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$206'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$207'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$208'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$209'. removing unused `$_AND_' cell `$auto$simplemap.cc:277:simplemap_mux$210'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$230'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$231'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$232'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$233'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$234'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$235'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$236'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$237'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$238'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$239'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$240'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$241'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$242'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$243'. removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$244'. removed 243 unused temporary wires. Removed 95 unused cells and 350 unused wires. 2.22.6. Rerunning OPT passes. (Removed registers in this run.) 2.22.7. Running ICE40 specific optimizations. 2.22.8. Executing OPT_EXPR pass (perform const folding). 2.22.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.22.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.22.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 95 unused cells and 350 unused wires. 2.22.12. Finished OPT passes. (There is nothing left to do.) 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. No more expansions possible. 2.24. Executing ABC pass (technology mapping using ABC). 2.24.1. Extracting gate netlist of module `\top' to `/input.blif'.. Extracted 64 gates and 93 wires to a netlist network with 28 inputs and 16 outputs. 2.24.1.1. Executing ABC. Running ABC command: abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + write_blif /output.blif 2.24.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 50 ABC RESULTS: internal signals: 49 ABC RESULTS: input signals: 28 ABC RESULTS: output signals: 16 Removing temp directory. Removed 0 unused cells and 59 unused wires. 2.25. Executing TECHMAP pass (map to technology primitives). 2.25.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NN0_'. Generating RTLIL representation for module `\$_DFF_NN1_'. Generating RTLIL representation for module `\$_DFF_PN0_'. Generating RTLIL representation for module `\$_DFF_PN1_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$__DFFE_NN0'. Generating RTLIL representation for module `\$__DFFE_NN1'. Generating RTLIL representation for module `\$__DFFE_PN0'. Generating RTLIL representation for module `\$__DFFE_PN1'. Generating RTLIL representation for module `\$__DFFE_NP0'. Generating RTLIL representation for module `\$__DFFE_NP1'. Generating RTLIL representation for module `\$__DFFE_PP0'. Generating RTLIL representation for module `\$__DFFE_PP1'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 2.25.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'00000001 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'00000001'. 2.25.3. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$811 using $paramod\$lut\WIDTH=3\LUT=8'00000001. 2.25.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 4 Parameter \LUT = 16'1000000000000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'1000000000000000'. 2.25.5. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$810 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$809 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. 2.25.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 4 Parameter \LUT = 16'0100000000000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0100000000000000'. 2.25.7. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$808 using $paramod\$lut\WIDTH=4\LUT=16'0100000000000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$807 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. 2.25.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 2 Parameter \LUT = 4'0100 Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'0100'. 2.25.9. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$806 using $paramod\$lut\WIDTH=2\LUT=4'0100. 2.25.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 4 Parameter \LUT = 16'0001000000000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0001000000000000'. 2.25.11. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$815 using $paramod\$lut\WIDTH=4\LUT=16'0001000000000000. 2.25.12. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'10000000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'10000000'. 2.25.13. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$816 using $paramod\$lut\WIDTH=3\LUT=8'10000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$814 using $paramod\$lut\WIDTH=4\LUT=16'0001000000000000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$813 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000. 2.25.14. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'11110100 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'11110100'. 2.25.15. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$817 using $paramod\$lut\WIDTH=3\LUT=8'11110100. 2.25.16. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'11001010 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'11001010'. 2.25.17. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$821 using $paramod\$lut\WIDTH=3\LUT=8'11001010. 2.25.18. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 2 Parameter \LUT = 4'1011 Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'1011'. 2.25.19. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$825 using $paramod\$lut\WIDTH=2\LUT=4'1011. 2.25.20. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 1 Parameter \LUT = 2'01 Generating RTLIL representation for module `$paramod\$lut\WIDTH=1\LUT=2'01'. 2.25.21. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$826 using $paramod\$lut\WIDTH=1\LUT=2'01. 2.25.22. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 3 Parameter \LUT = 8'00010000 Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'00010000'. 2.25.23. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$818 using $paramod\$lut\WIDTH=3\LUT=8'00010000. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$819 using $paramod\$lut\WIDTH=2\LUT=4'1011. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$829 using $paramod\$lut\WIDTH=1\LUT=2'01. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$827 using $paramod\$lut\WIDTH=1\LUT=2'01. 2.25.24. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'. Parameter \WIDTH = 2 Parameter \LUT = 4'1110 Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'1110'. 2.25.25. Continuing TECHMAP pass. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$823 using $paramod\$lut\WIDTH=2\LUT=4'1110. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$812 using $paramod\$lut\WIDTH=3\LUT=8'11110100. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$830 using $paramod\$lut\WIDTH=1\LUT=2'01. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$820 using $paramod\$lut\WIDTH=3\LUT=8'11110100. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$824 using $paramod\$lut\WIDTH=1\LUT=2'01. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$822 using $paramod\$lut\WIDTH=3\LUT=8'11001010. Mapping top.$abc$805$auto$blifparse.cc:492:parse_blif$828 using $paramod\$lut\WIDTH=1\LUT=2'01. No more expansions possible. Removed 0 unused cells and 50 unused wires. 2.26. Executing HIERARCHY pass (managing design hierarchy). 2.26.1. Analyzing design hierarchy.. Top module: \top 2.26.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 2.26.3. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'0100 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'0100'. 2.26.4. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.5. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0100000000000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0100000000000000'. 2.26.6. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.7. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.8. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'00000001 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'00000001'. 2.26.9. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11110100 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11110100'. 2.26.10. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'1000000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'1000000000000000'. 2.26.11. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0001000000000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0001000000000000'. 2.26.12. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0001000000000000 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0001000000000000'. 2.26.13. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'10000000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'10000000'. 2.26.14. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11110100 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11110100'. 2.26.15. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'00010000 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'00010000'. 2.26.16. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'1011 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'1011'. 2.26.17. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11110100 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11110100'. 2.26.18. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11001010 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11001010'. 2.26.19. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 8'11001010 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=8'11001010'. 2.26.20. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'1110 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'1110'. 2.26.21. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.22. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 4'1011 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=4'1011'. 2.26.23. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.24. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.25. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.26. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.27. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 2'01 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=2'01'. 2.26.28. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Generating RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.29. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.30. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.31. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.32. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.33. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.34. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.35. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.36. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.37. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.38. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.39. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.40. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.41. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.42. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.43. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.44. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.45. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.46. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.47. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.48. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.49. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.50. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.51. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.52. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.53. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.54. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.55. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.56. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.57. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.58. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.59. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.60. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.61. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.62. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.63. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.64. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.65. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.26.66. Executing AST frontend in derive mode using pre-parsed AST for module `\SB_LUT4'. Parameter \LUT_INIT = 16'0110100110010110 Found cached RTLIL representation for module `$paramod\SB_LUT4\LUT_INIT=16'0110100110010110'. 2.27. Printing statistics. === top === Number of wires: 48 Number of wire bits: 179 Number of public wires: 16 Number of public wire bits: 55 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 162 SB_CARRY 49 SB_DFF 15 SB_DFFE 4 SB_DFFESR 15 SB_DFFSR 15 SB_LUT4 64 2.28. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 2.29. Executing BLIF backend. End of script. Logfile hash: b2348668fd CPU: user 0.67s system 0.03s, MEM: 55.56 MB total, 47.36 MB resident Yosys 0.8 (git sha1 UNKNOWN, c++ 8.1 -O2 -fno-strict-aliasing -fPIC -Os) Time spent: 42% 9x read_verilog (0 sec), 9% 1x share (0 sec), ... arachne-pnr -d 1k -o example.asc -p ice40hx1k-evb.pcf example.blif -P vq100 seed: 1 device: 1k read_chipdb +/share/arachne-pnr/chipdb-1k.bin... supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100 read_blif example.blif... prune... read_pcf ice40hx1k-evb.pcf... instantiate_io... pack... After packing: IOs 5 / 72 GBs 0 / 8 GB_IOs 0 / 8 LCs 89 / 1280 DFF 16 CARRY 20 CARRY, DFF 33 DFF PASS 3 CARRY PASS 6 BRAMs 0 / 16 WARMBOOTs 0 / 1 PLLs 0 / 0 place_constraints... promote_globals... promoted clk_24KHz, 38 / 38 promoted $abc$805$n64, 17 / 18 promoted $0\LED1_m1_r[0:0], 16 / 16 promoted $abc$805$n66, 13 / 13 promoted CLK$2, 12 / 12 promoted 5 nets 2 sr/we 1 cen/wclke 2 clk 5 globals 2 sr/we 1 cen/wclke 2 clk realize_constants... realized 1 place... initial wire length = 554 at iteration #50: temp = 5.45421, wire length = 363 at iteration #100: temp = 2.28052, wire length = 260 at iteration #150: temp = 0.488208, wire length = 128 final wire length = 113 After placement: PIOs 8 / 72 PLBs 23 / 160 BRAMs 0 / 16 place time 0.22s route... pass 1, 0 shared. After routing: span_4 42 / 6944 span_12 14 / 1440 route time 0.08s write_txt example.asc... icetime -d hx1k -mtr example.rpt example.asc icepack example.asc example.bin // Reading input .asc file.. // Reading 1k chipdb file.. // Creating timing netlist.. // Timing estimate: 7.52 ns (132.97 MHz) rm example.blif example.asc gmake[1]: Leaving directory '/construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb' /usr/bin/env XDG_DATA_HOME=/construction/devel/lattice-ice40-examples-hx1k XDG_CONFIG_HOME=/construction/devel/lattice-ice40-examples-hx1k HOME=/construction/devel/lattice-ice40-examples-hx1k TMPDIR="/tmp" PATH=/construction/devel/lattice-ice40-examples-hx1k/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin NO_PIE=yes MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES CCVER=gcc80 PREFIX=/usr/local LOCALBASE=/usr/local NOPROFILE=1 CC="cc" CFLAGS="-pipe -O2 -fno-strict-aliasing " CPP="cpp" CPPFLAGS="" LDFLAGS=" " LIBS="" CXX="c++" CXXFLAGS=" -pipe -O2 -fno-strict-aliasing " MANPREFIX="/usr/local" BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" gmake -f Makefile -j5 -C /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video gmake[1]: Entering directory '/construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video' gmake[1]: Nothing to be done for 'all'. gmake[1]: Leaving directory '/construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video' -------------------------------------------------------------------------------- -- Phase: run-depends -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Phase: stage -------------------------------------------------------------------------------- ===> Staging for lattice-ice40-examples-hx1k-g20180310 ===> Generating temporary packing list install -m 0644 /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb/example.v /construction/devel/lattice-ice40-examples-hx1k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-blinky.v install -m 0644 /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb/example.rpt /construction/devel/lattice-ice40-examples-hx1k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-blinky.rpt install -m 0644 /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40hx1k-evb/example.bin /construction/devel/lattice-ice40-examples-hx1k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-blinky.bin install -m 0644 /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video/example.v /construction/devel/lattice-ice40-examples-hx1k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-vga-ps2.v install -m 0644 /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video/example.rpt /construction/devel/lattice-ice40-examples-hx1k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-vga-ps2.rpt install -m 0644 /construction/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/demo/ice40-io-video/example.bin /construction/devel/lattice-ice40-examples-hx1k/stage/usr/local/share/examples/lattice-ice40-olimex/ice40hx1k-vga-ps2.bin ====> Compressing man pages (compress-man) -------------------------------------------------------------------------------- -- Phase: package -------------------------------------------------------------------------------- ===> Building package for lattice-ice40-examples-hx1k-g20180310 file sizes/checksums [9]: . done packing files [9]: . done packing directories [0]: . done -------------------------------------------------- -- Termination -------------------------------------------------- Finished: Sunday, 7 JUL 2019 at 17:44:25 UTC Duration: 00:00:53